Patents Examined by Jonathan C Langman
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Patent number: 7867620Abstract: A composite plate comprising CNT bundles with high thermal conductivity is formed by the method comprising preparing a CNT growth substrate, depositing a CNT growth catalyst on the CNT growth substrate, preparing a wafer with etched through via arrays, placing the wafer with the etched through via arrays over the CNT growth substrate with the CNT growth catalyst, growing CNT bundles in the etched through via arrays on the wafer over the CNT growth substrate with the CNT growth catalyst in a CVD chamber to form a wafer matrix CNT composite structure; and removing the CNT growth substrate from the wafer matrix CNT composite structure. The formed composite plate comprising CNT bundles with high thermal conductivity has improved CTE silicon match, has a more effective thermal conductivity than a silicon matrix or Cu or Cu alloy substrate, and contains nanotubes that remain vertical.Type: GrantFiled: July 24, 2007Date of Patent: January 11, 2011Assignee: Rockwell Collins, Inc.Inventors: Oizhou Yao, Allen W. Jones, Don L. Landt, Gary E. Lehtola
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Patent number: 7838107Abstract: An aluminum/silicon carbide composite prepared by infiltrating a flat silicon carbide porous body with a metal containing aluminum as the main component, including an aluminum alloy layer made of a metal containing aluminum as the main component on both principal planes, and one principal plane is bonded to a circuit plate and the other principal plane is utilized as a radiation plane. The silicon carbide porous body is formed or machined into a convexly bowed shape, and after infiltration with the metal containing aluminum as the main component, the aluminum alloy layer on the radiation plane is further machined to form the bow shape. The aluminum/silicon carbide composite is suitable as a base plate for a ceramic circuit plate on which semiconductor components are mounted, for which high reliability is required.Type: GrantFiled: September 7, 2005Date of Patent: November 23, 2010Assignee: Denki Kagaku Kogyo Kabushiki KaishaInventors: Goh Iwamoto, Hideki Hirotsuru, Kazunori Hirahara
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Patent number: 7824782Abstract: A molded article located in the beam path of a radar device has only a slight amount of radio transmission loss and has a metallic color. The molded article comprises a substrate and a layer of ceramic material with which the external surface of the substrate is coated. The ceramic material includes nitride ceramics, oxide ceramics, carbide ceramics, and mixtures thereof. The ceramic material includes titanium nitride and/or aluminum nitride.Type: GrantFiled: August 4, 2004Date of Patent: November 2, 2010Assignee: Toyota Jidosha Kabushiki KaishaInventors: Itsuo Kamiya, Sumio Kamiya, Izumi Takahashi
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Patent number: 7816013Abstract: A wafer has a rare earth fluoride coating disposed, typically sprayed on a substrate as an outermost layer, the rare earth fluoride being selected from lanthanoid fluorides, yttrium fluoride, and scandium fluoride. It is useful as a dummy wafer in a plasma etching or deposition system.Type: GrantFiled: December 2, 2008Date of Patent: October 19, 2010Assignee: Shin-Etsu Chemical Co., Ltd.Inventors: Toshihiko Tsukatani, Masaru Konya, Noriaki Hamaya, Hajime Nakano, Takao Maeda
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Patent number: 7794842Abstract: The present invention provides a high resistivity, high quality, large size SiC single crystal, SiC single crystal wafer, and method of production of the same, that is, a silicon carbide single crystal containing uncompensated impurities in an atomic number density of 1 ×1015/cm3 or more and containing vanadium in an amount less than said uncompensated impurity concentration, silicon carbide single crystal wafer obtained by processing and polishing the silicon carbide single crystal and having an electrical resistivity at room temperature of 5×103 ?cm or more, and a method of production of a silicon carbide single crystal.Type: GrantFiled: December 27, 2004Date of Patent: September 14, 2010Assignee: Nippon Steel CorporationInventors: Masashi Nakabayashi, Tatsuo Fujimoto, Mitsuru Sawamura, Noboru Ohtani
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Patent number: 7781066Abstract: A multilayer ceramic substrate includes a base layer made of an aggregate of a first powder including a glass material and a first ceramic material, a constraining layer made of an aggregate of a second powder including a second ceramic material that is not sintered at a temperature at which the glass material melts, an intermediate layer made of an aggregate of a third powder including a viscosity-reducing material that reduces the viscosity of the melt of the glass material, and a conductive film disposed along at least one main surface of the base layer, the constraining layer, and the intermediate layer. The intermediate layer is arranged such that one main surface thereof is in contact with the base layer and the other main surface thereof is in contact with the constraining layer. At least a portion of the first powder is in a sintered state.Type: GrantFiled: June 20, 2007Date of Patent: August 24, 2010Assignee: Murata Manufacturing Co., Ltd.Inventor: Shuya Nakao
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Patent number: 7781065Abstract: A multilayer ceramic substrate includes a base material layer including an aggregate of first particles containing a crystallized glass material and a first ceramic material, a constraining layer including an aggregate of second particles containing a second ceramic material that does not sinter at a temperature at which the crystallized glass material is melted, an intercalating layer including an aggregate of third particles containing a viscosity-decreasing substance that decreases the viscosity the melted crystallized glass material, and conductive films arranged along a main surface of at least one of the base material layer, the constraining layer, and the intercalated layer. The multilayer ceramic substrate also includes conductive films provided along a main surface of at least one of the base material layer, the constraining layer, and the intercalated layer.Type: GrantFiled: March 27, 2007Date of Patent: August 24, 2010Assignee: Murata Manufacturing Co., Ltd.Inventor: Shuya Nakao
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Patent number: 7781067Abstract: A semiconducting structure having a glass substrate. In one embodiment, the glass substrate has a softening temperature of at least about 750° C. The structure includes a nucleation layer formed on a surface of the substrate, a template layer deposited on the nucleation layer by one of ion assisted beam deposition and reactive ion beam deposition, at least on biaxially oriented buffer layer epitaxially deposited on the template layer, and a biaxially oriented semiconducting layer epitaxially deposited on the buffer layer. A method of making the semiconducting structure is also described.Type: GrantFiled: October 17, 2006Date of Patent: August 24, 2010Assignee: Los Alamos National Security, LLCInventor: Alp T. Findikoglu
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Patent number: 7776425Abstract: A non-vacuum-based, non-collodial chemistry-based method of synthesizing metal nanoparticles and nanoparticle-nanostructured material composites obtained by that method. An embodiment of the method of this invention for fabricating a nanoparticle-nanostructured material composite and synthesizing nanoparticles includes preparing a nanostructured/nanotextured material, and, contacting the nanostructured/nanotextured material with a solution. Nanoparticles are synthesized on the nanostructured/nanotextured material as a result of the contact. The method of the present invention can be utilized to fabricate SPR and SERS substrates for sensing and detection. Additional systems based on this approach (e.g., surface plasmon resonance absorption and alloying sensors and nanocatalysts) are described.Type: GrantFiled: January 21, 2004Date of Patent: August 17, 2010Assignee: The Penn State Research FoundationInventors: Ali Kaan Kalkan, Stephen J. Fonash
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Patent number: 7767305Abstract: Tantalum-based ceramics are suitable for use in thermal protection systems. These composite structures have high efficiency surfaces (low catalytic efficiency and high emittance), thereby reducing heat flux to a spacecraft during planetary re-entry. These ceramics contain tantalum disilicide, molybdenum disilicide and borosilicate glass. The components are milled, along with a processing aid, then applied to a surface of a porous substrate, such as a fibrous silica or carbon substrate. Following application, the coating is then sintered on the substrate. The composite structure is substantially impervious to hot gas penetration and capable of surviving high heat fluxes at temperatures approaching 3000° F. and above.Type: GrantFiled: January 14, 2004Date of Patent: August 3, 2010Assignee: The United States of America as represented by the Administrator of the National Aeronautics and Space Administration (NASA)Inventors: David A. Stewart, Daniel B. Leiser, Robert R. DiFiore, Victor W. Katvala
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Patent number: 7749622Abstract: A multilayer film-coated substrate having the stress of the film relaxed by depositing a multilayer film comprising a metal oxide film and a silicon oxide film on a substrate at a high speed by a sputtering method using a conductive sputtering material, and a process for producing a multilayer film-coated substrate having such a low stress, are presented. A multilayer film-coated substrate comprising a substrate and at least a metal oxide film and a silicon oxide film laminated thereon repeatedly at least once, wherein at least one layer of said metal oxide film is a metal oxide film deposited by sputtering by using, as the target material, a metal oxide MOX which is deficient in oxygen than the stoichiometric composition, to have the oxygen deficiency resolved, and the stress of the multilayer film is from ?100 MPa to +100 MPa.Type: GrantFiled: April 21, 2005Date of Patent: July 6, 2010Assignee: Asahi Glass Company, LimitedInventors: Tomohiro Yamada, Eiji Shidoji, Akira Mitsui, Takuji Oyama, Toshihisa Kamiyama
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Patent number: 7732054Abstract: A method for preparing a ZnO nanocrystal directly on a silicon substrate includes the steps of: (S1) forming a Zn—Si—O composite thin film on the silicon substrate; and (S2) thermally treating the obtained thin film. Particularly, ZnO nanocrystals are formed in an amorphous Zn—Si—O composite thin film by controlling the composition of the Zn—Si—O composite thin film and heating temperature thereof. With the present invention method for preparing a ZnO nanocrystal directly on a silicon substrate, more possibilities are opened up for the applications of ZnO nanocrystals to an optoelectronic device in use of a silicon substrate.Type: GrantFiled: December 28, 2007Date of Patent: June 8, 2010Assignee: Korea Institute of Science and TechnologyInventors: Young Hwan Kim, Woon Jo Cho, Seong Kim, II, Chun Keun Kim, Yong Tae Kim
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Patent number: 7704612Abstract: The long-term use of a conventional jig for calcining an electronic component arises a problem such as peel-off of a zirconia surface layer. Even if the performance is not deteriorated in the short-term use, the zirconia surface layer reacts with the electronic component to shorten the life of the jig for calcining the electronic component when the use is prolonged for a longer period of time. A jig for calcining an electronic component is provided which is stable after use of a longer period of time by suitably setting the composition of a zirconia surface layer. For example, in the zirconia surface layer containing zirconia particles and a partially fused-bonding agent, an amount of calcia is made to be 4 to 15% in weight.Type: GrantFiled: March 31, 2005Date of Patent: April 27, 2010Assignee: Mitsui Mining & Smelting Co., Ltd.Inventors: Hitoshi Kajino, Tatsuhiko Uchida
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Patent number: 7700202Abstract: A precursor formulation of a silicon carbide material that includes a ceramic material and a boron-11 compound. The ceramic material may include silicon and carbon and, optionally, oxygen, nitrogen, titanium, zirconium, aluminum, or mixtures thereof. The boron-11 compound may be a boron-11 isotope of boron oxide, boron hydride, boron hydroxide, boron carbide, boron nitride, boron trichloride, boron trifluoride, boron metal, or mixtures thereof. A material for use in a nuclear reactor component is also disclosed, as are such components, as well as a method of producing the material.Type: GrantFiled: February 16, 2006Date of Patent: April 20, 2010Assignee: Alliant Techsystems Inc.Inventors: Timothy E. Easler, Andrew Szweda, Eric Stein
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Patent number: 7678458Abstract: A wafer chuck for use in a lithographic apparatus, which includes a low-thermal expansion glass ceramic substrate, a silicon silicon carbide layer, and a bonding layer comprising silicate having a strength of at least about 5 megapascals, the bonding layer attaching the silicon silicon carbide layer to the substrate is described. Also, a method of forming a wafer chuck for use in a lithographic apparatus, which includes coating a portion of one or both of a low-thermal expansion glass ceramic substrate and a silicon silicon carbide layer with a bonding solution, and contacting the substrate and the silicon silicon carbide layer to bond the substrate and the silicon silicon carbide layer together is described.Type: GrantFiled: January 24, 2007Date of Patent: March 16, 2010Assignee: ASML Holding N.V.Inventors: Matthew Lipson, Robert D. Harned, Geoffrey O'Connor, Timothy O'Neil
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Patent number: 7670689Abstract: The sulfidation resistance of a silver-base material coating is further improved by making a concentration gradient of silver, oxygen and of one or more oxidizable alloying elements that may be present in the material, from the free surface of the coating up to a depth comprised between 10 nm and 1 ?m and more particularly between 100 nm and 1 ?m. Thus, the coating comprises a stack of one main layer made from silver-base material and of one oxidized thin film. The thin film, with a thickness comprised between 10 nm and 1 ?m, thus presents a decreasing silver concentration gradient from the interface between the thin film and the main layer to the free surface of the thin film. Deposition of the coating on a support can be achieved by two successive physical vapor deposition steps, and more particularly by magnetron cathode sputtering.Type: GrantFiled: October 23, 2006Date of Patent: March 2, 2010Assignee: Commissariat a l'Energie AtomiqueInventors: Denis Camel, Laurent Bedel, Frédéric Sanchette, Cédric Ducros
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Patent number: 7666513Abstract: A method of joining two silicon members, the adhesive used for the method, and the joined product, especially a silicon tower for supporting multiple silicon wafers. A flowable adhesive is prepared comprising silicon particles of size less than 100 ?m and preferably less than 100 nm and a silica bridging agent, such as a spin-on glass. Nano-silicon crystallites of about 20 nm size may be formed by CVD. Larger particles may be milled from virgin polysilicon. If necessary, a retardant such as a heavy, preferably water-insoluble alcohol such as terpineol is added to slow setting of the adhesive at room temperature. The mixture is applied to the joining areas. The silicon parts are assembled and annealed at a temperature sufficient to link the silica, preferably at 900° C. to 1100° C. for nano-silicon but higher for milled silicon.Type: GrantFiled: June 1, 2006Date of Patent: February 23, 2010Assignee: Integrated Materials, Inc.Inventors: James E. Boyle, Raanan Zehavi, Amnon Chalzel
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Patent number: 7662488Abstract: A nitride-based semiconductor substrate having a diameter of 25 mm or more, a thickness of 250 micrometers or more, and an optical absorption coefficient of less than 7 cm?1 to light with a wavelength of 380 nm or more. The nitride-based semiconductor substrate is made by the HVPE method that uses gallium chloride obtained by reacting a Ga melt with a hydrogen chloride gas. The Ga melt is contacted with the hydrogen chloride gas for one minute or more to produce the gallium chloride.Type: GrantFiled: February 21, 2006Date of Patent: February 16, 2010Assignee: Hitachi Cable, Ltd.Inventor: Yuichi Oshima
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Patent number: 7655315Abstract: A silicon wafer includes a principal face for forming electronic devices; an end region; and a tapered region which is located between the principal face and the end region, in which the thickness of the silicon wafer is gradually reduced, and which has a slope that makes an angle of greater than zero degree and less than 9.5 degrees or an angle of greater than 19 degrees with the principal face. An SOI wafer prepared by forming a buried oxide layer in a silicon wafer includes a principal face, end region, and tapered region that are substantially the same as those described above. A method for manufacturing an SOI wafer includes the steps of implanting oxygen ions into a silicon wafer; and heat-treating the resulting silicon wafer such that a buried oxide layer is formed in the silicon wafer.Type: GrantFiled: January 13, 2006Date of Patent: February 2, 2010Assignee: Sumco CorporationInventors: Eiji Kamiyama, Seiichi Nakamura, Tetsuya Nakai
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Patent number: 7655327Abstract: Compositions comprising a single-phase rare-earth dielectric disposed on a substrate. Embodiments of the present invention provide the basis for high-K gate dielectrics in conventional integrated circuits and high-K buried dielectrics as part of a semiconductor-on-insulator wafer structure.Type: GrantFiled: October 19, 2005Date of Patent: February 2, 2010Assignee: Translucent, Inc.Inventor: Petar Atanackovic