Abstract: According to embodiments, a light emitting display device includes a light emitting diode (LED) positioned on a substrate and including an emission layer, a pixel definition layer including an opening corresponding to the emission layer, and a plurality of light-shielding linear patterns positioned on the pixel definition layer and the emission layer and extending in a first direction. The plurality of light-shielding linear patterns include a recess portion of a concave shape.

Abstract: An integrated circuit device includes a first-type active-region semiconductor structure extending and a second-type active-region semiconductor structure both extending in a first direction. The second-type active-region semiconductor structure is stacked with the first-type active-region semiconductor structure. The integrated circuit device also includes a front-side conductive layer above the two active-region semiconductor structures and a back-side conductive layer below the two active-region semiconductor structures. The integrated circuit device still includes a front-side power rail extending in the second direction in the front-side conductive layer and a back-side power rail extending in the second direction in the back-side conductive layer. The integrated circuit device further includes a first source conductive segment connected to the front-side power rail and a second source conductive segment connected to the back-side power rail.

Abstract: An integrated circuit (IC) structure includes a gate structure, source/drain epitaxial structures, a front-side interconnection structure, a backside dielectric layer, and a backside via. The source/drain epitaxial structures are respectively on opposite sides of the gate structure. The front-side interconnection structure is on front-sides of the source/drain epitaxial structures. The backside dielectric layer is on backsides of the source/drain epitaxial structures. The backside via extends through the backside dielectric layer to one of the source/drain epitaxial structures, and has a maximal lateral dimension larger than a lateral dimension of the source/drain epitaxial structure.

Abstract: A heterogeneous epitaxial structure formed on a SiC (silicon carbide) substrate. An intermediate layer comprising AlN is formed overlying the SiC substrate. The surface of the intermediate layer comprises AlN formed by lateral epitaxial growth. The lateral epitaxial growth merges to form the surface comprising a MELO layer (merged epitaxial lateral overgrowth). The intermediate layer includes a carbon layer underlying the MELO layer. At least one device layer comprising GaN (gallium nitride) is formed overlying the surface of the intermediate layer in which one or more semiconductor devices are formed. The carbon layer is heated to fracture portions of the intermediate layer to separate the SiC substrate from the intermediate layer. The SiC substrate is not consumed by the separation thereby allowing perpetual reuse in semiconductor wafer processing.

Abstract: Provided is a solid-state imaging device that readily accommodates a design change of a pixel chip or a circuit chip. The solid-state imaging device according to the present technology includes a pixel chip including a pixel having a photoelectric conversion element, at least one circuit chip including a circuit configured to process a signal generated in the pixel, and a connecting substrate electrically connecting the pixel chip and the circuit chip, in which the pixel chip, the connecting substrate, and the circuit chip are stacked in this order. It is possible to provide a solid-state imaging device that readily accommodates a design change of a pixel chip or a circuit chip on the basis of the solid-state imaging device according to the present technology.

Abstract: The present disclosure provides a display panel and a display apparatus. The display panel includes a first electrode layer, an electron transport layer, a light emitting layer, a hole transport layer, a hole injection layer, and a second electrode layer, which are sequentially stacked, a material of the hole injection layer includes a first metal oxide and a second metal oxide, which contain the same metal element, the number of outermost electrons of the metal element in the first metal oxide is different from the number of outermost electrons of the metal in the second metal oxide. In addition, the hole injection layer further includes a metal M and a third metal oxide MOy, the third metal oxide MOy is formed by an oxidation-reduction reaction between the metal M and the first metal oxide. The hole injection layer may be of a single layer or a multi-layer structure.

Abstract: A semiconductor device includes a substrate having first and second active patterns therein, which are spaced apart from each other. The first active pattern has a top surface that is elevated relative to a top surface of the second active pattern. A channel semiconductor layer is provided on the top surface of the first active pattern. A first gate pattern is provided, which includes a first insulating pattern, on the channel semiconductor layer. A second gate pattern is provided, which includes a second insulating pattern having a thickness greater than a thickness of the first insulating pattern, on the top surface of the second active pattern.

Abstract: Disclosed herein are techniques for micro-light emitting diodes (micro-LEDs). According to certain embodiments, a micro-LED device includes a micro-LED comprising a semiconductor mesa structure configured to emit light, a spacer layer on the micro-LED, and a micro-lens on the spacer layer and configured to extract and collimate the light emitted by the micro-LED, where a thickness of the spacer layer is selected such that a focal point of the micro-lens is at a front surface of the semiconductor mesa structure.

Abstract: An electronic device and a manufacturing method thereof are disclosed. The electronic device includes a substrate, an electronic element, a barrier layer, a light absorbing layer, and a filter layer. The electronic element is disposed on the substrate. The barrier layer is disposed on the substrate and surrounds a side surface of the electronic element. The light absorbing layer is disposed on the barrier layer. The filter layer is disposed on the electronic element.

Abstract: An integrated circuit (IC) device is described. The IC device includes a semiconductor-on-insulator (SOI) substrate having a first-type diffusion region. The IC device also includes a first, first-type transistor on the first-type diffusion region. The IC device further includes a second, first-type transistor on the first-type diffusion region. The IC device also includes a first, second-type implant region. The first, second-type implant region includes a gate overlap region partially overlapped with a gate region of the second, first-type transistor to provide a body contact of the second, first-type transistor and to couple a source region of the second, first-type transistor to a drain region of the first, first-type transistor in series.

Abstract: A method of forming a semiconductor structure includes providing a substrate with an array region, a peripheral region, and a transition region between the array region and the peripheral region. A patterned floating gate layer is formed on the array region and the peripheral region, and a stacked layer is conformally formed on the substrate, wherein a recess is formed over the transition region. A photoresist layer is formed on the substrate, and the photoresist layer is patterned to form an array region pattern on the stacked layer of the array region, wherein a portion of the photoresist layer remains at the bottom of the recess, and a recess pattern is formed. The array region pattern and the recess pattern are sequentially transferred to the stacked layer, the patterned floating gate layer and the substrate to form a plurality of arrays and a pair of blocking structures.

Abstract: Provided are a color conversion structure, a display apparatus, and a method of manufacturing a color conversion structure. The color conversion structure includes a bank structure including a groove, a color conversion layer accommodated in the groove, and a cover layer provided on the color conversion layer.

Abstract: A package includes a mounting surface on which an electronic component is to be mounted, a cavity, and an attachment surface to which a lid is to be attached through an adhesive layer. The package includes: a bottom containing ceramics and having the mounting surface; and a frame containing ceramics and having the attachment surface. The attachment surface of the frame includes an inner end adjacent to the cavity and an outer end opposite to the inner end in at least one cross-sectional view spanning an inside and an outside of the cavity, the attachment surface having a protruding shape protruding in a thickness direction. At least one of the inner end or the outer end is made lower than a most protruding portion of the protruding shape by 10 ?m or more.

Abstract: Provided is an electronic device including: a biometric information sensing layer including a sensor; an optical pattern layer disposed on the biometric information sensing layer, and including a plurality of transmission parts and a light shielding part; and a display layer disposed on the optical pattern layer. When a fill factor (FF) of the sensor, which is a ratio of the amount of light received by the sensor to the total amount of light incident onto the sensor, is about 10% to about 70%, a field of view (FOV) of light incident onto the sensor is about 15° to about 30°.

Abstract: A texture recognition module and a display device, the texture recognition module includes a texture recognition substrate including a texture acquisition region and a peripheral region at least partially surrounding the texture acquisition region, and the texture recognition substrate includes a base substrate, multiple photosensitive sub-pixels, an optical module layer and a support layer, the multiple photosensitive sub-pixels are arranged on the base substrate and located in the texture acquisition region, each photosensitive sub-pixel includes a photosensitive element and for texture acquisition, the optical module layer is arranged on a side of the multiple photosensitive sub-pixels away from the base substrate and configured to adjust light transmission, and the support layer is arranged on a side of the optical module layer away from the base substrate and includes an acquisition opening which exposes the multiple photosensitive sub-pixels. The texture recognition module has a better stability.

Abstract: An image sensor includes a first color filter disposed on a first photodiode, a first grid, and a first micro lens disposed on the first color filter and the first grid. The first grid includes a first main portion and a first shielding portion extended from the first main portion. The first main portion surrounds the first color filter and the first shielding portion partially covers the first color filter such that a first cavity defined by the first shielding portion is configured over the first color filter. The first color filter or the first micro lens includes a first protruding portion filled in the first cavity, and a width of the first protruding portion is in a range from 0.1 pixel size to 0.8 pixel size. A manufacturing method of an image sensor is also disclosed.

Abstract: The present invention provides a reduced-height image-capturing module, which includes a lens assembly, an image-sensing chip, a carrier base and a circuit substrate. The carrier base has a base body, two extending plate bodies extending and a base groove recessed. A lower portion of the base body enters a through opening of the circuit substrate, and the two extending plate bodies cross over the through opening of the circuit substrate and are disposed on an upper surface of the circuit substrate. The image-sensing chip is disposed on a recessed bottom surface of the base groove which is not at the same level as the upper surface of the circuit substrate, so that the recessed bottom surface is lower than the upper surface of the circuit substrate. The lens assembly is disposed on the upper portion of the base body and corresponds to the image-sensing chip.

Abstract: A backlight module and a display device are disclosed. The backlight module includes a light board and a heat dissipation structure. Multiple light-emitting elements are arranged in a matrix on the light board. The heat dissipation structure includes a first control layer arranged on a side of the light board facing away from the light-emitting elements, and a second control layer opposite to the first control layer. There is a gap between the first control layer and second control layer, and there is disposed a coolant droplet in the gap. When a light-emitting element satisfies a first heating condition, the first control layer and second control layer control a coolant droplet to move to a position underneath the light-emitting element. When the light-emitting element satisfies a second heating condition, the first control layer and second control layer control the coolant droplet to leave the position underneath the light-emitting element.

Abstract: The present disclosure relates to development of microdevices on a substrate that can be released and transferred to a system substrate. The disclosure further relates to methods to integrate anchors to hold a microdevice to a substrate. The microdevices are in different configurations with respect to anchors, release layers, buffers layers and substrate.

Abstract: An integrated circuit device includes a first cell and a second cell apart from each other in a first lateral direction on a substrate, the first cell and the second cell each including a plurality of gate lines, an inter-cell isolation region between the first cell and the second cell, the inter-cell isolation region extending in a second lateral direction, a power line including portions overlapping a cell boundary of each of the first cell and the second cell in a vertical direction and a portion overlapping the inter-cell isolation region in the vertical direction, a plurality of dummy gate insulation lines, a bridge insulating pattern in contact with an end portion of each of the plurality of dummy gate insulation lines, and a via power rail passing through the bridge insulating pattern, the via power rail being connected to the power line.