Patents Examined by Jonathan Han
  • Patent number: 10693055
    Abstract: Magnetic random access memory (MRAM) devices are provided. The MRAM devices may include a magnetic tunnel junction (MTJ) including a free layer and a pinned layer sequentially stacked in a vertical direction and a conductive layer adjacent to the free layer of the MTJ. The conductive layer may include a horizontal portion and first and second protruding portions that protrude away from the horizontal portion and are spaced apart from each other in a horizontal direction that is perpendicular to the vertical direction. A side of the free layer and a side of the horizontal portion may form a straight side.
    Type: Grant
    Filed: November 28, 2018
    Date of Patent: June 23, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Kilho Lee, Gwanhyeob Koh, Yoonjong Song
  • Patent number: 10692806
    Abstract: A semiconductor arrangement includes a circuit board having a metallization layer with first and second conductor tracks. The first conductor track has a base section and first, second and third sections, the third section arranged between the first and second sections. The second conductor track has first and second sections. The first section of the second conductor track is arranged between the first and third sections of the first conductor track. The second section of the second conductor track is arranged between the second and third sections of the first conductor track. The third section of the first conductor track is arranged between the first and second sections of the second conductor track. First and second subsets of semiconductor chips are arranged on the first section of the second conductor track. Third and fourth subsets of semiconductor chips are arranged on the second section of the second conductor track.
    Type: Grant
    Filed: November 2, 2018
    Date of Patent: June 23, 2020
    Assignee: Infineon Technologies AG
    Inventors: Waldemar Jakobi, Christoph Koch
  • Patent number: 10686047
    Abstract: A semiconductor device includes a semiconductor substrate, a gate dielectric, a gate electrode and a pair of source/drain regions. The gate dielectric is disposed in the semiconductor substrate having a concave profile that defines an upper boundary lower than an upper surface of the semiconductor substrate. The gate electrode is disposed over the gate dielectric. The pair of source/drain regions are disposed on opposing sides of the gate dielectric.
    Type: Grant
    Filed: May 23, 2018
    Date of Patent: June 16, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Ta-Yuan Kung, Ruey-Hsin Liu, Chen-Liang Chu, Chih-Wen Yao, Ming-Ta Lei
  • Patent number: 10677974
    Abstract: A method for manufacturing a pattern structure includes preparing a wafer that has a plurality of fine patterns, generating a first trench by processing the wafer from a first surface to a first depth, and generating a second trench connected to the first trench by processing the wafer from a second surface which is opposite to the first surface to a second depth, thereby cutting the wafer.
    Type: Grant
    Filed: July 11, 2017
    Date of Patent: June 9, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Sunghoon Lee, Joonyong Park, Dongouk Kim, Jihyun Bae, Bongsu Shin, Dongsik Shim, Jaeseung Chung
  • Patent number: 10679866
    Abstract: A semiconductor package includes a carrier, at least and adhesive portion, a plurality of micro pins and a die. The carrier has a first surface and second surface opposite to the first surface. The adhesive portion is disposed on the first surface, and the plurality of the micro pins is disposed in the adhesive portions. The die is disposed on the remaining adhesive portion free of the micro pins.
    Type: Grant
    Filed: February 13, 2015
    Date of Patent: June 9, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chien-Ling Hwang, Bor-Ping Jang, Chung-Shi Liu, Hsin-Hung Liao, Ying-Jui Huang
  • Patent number: 10679967
    Abstract: Semiconductor device assemblies may include a carrier wafer and a thermoset adhesive on a surface of the carrier wafer. A metal barrier material may be located on the thermoset adhesive. A thermoplastic adhesive may be located on an opposite side of the metal barrier material from the thermoset adhesive. A device wafer may be located on an opposite side of the thermoplastic material from the metal barrier material. Semiconductor device processing systems may include a carrier wafer having a thermoset adhesive adhered to a surface thereof and a metal barrier material adhered to the thermoset adhesive opposite the carrier wafer. A laser apparatus may be located on an opposite side of the carrier wafer from the metal barrier material and positioned to aim a laser beam through the carrier wafer to impinge on the metal barrier material.
    Type: Grant
    Filed: January 10, 2019
    Date of Patent: June 9, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Andrew M. Bayless, Joseph M. Brand
  • Patent number: 10679631
    Abstract: Automatic generation of a chat bot from an API specification to carry out a dialogue with a user and invoke an API call described in the API specification. Based on input API specification, a conversational bot specification representing a dialog flow is constructed. A natural language expression is received and transformed into instructions based on the conversational bot specification. Based on the instructions, a natural language prompt to the user and executable computer code for invoking the API call may be generated.
    Type: Grant
    Filed: June 6, 2019
    Date of Patent: June 9, 2020
    Assignee: International Business Machines Corporation
    Inventors: Martin Hirzel, Louis Mandel, Avraham E. Shinnar, Jerome Simeon, Mandana Vaziri, Charles Wiecha
  • Patent number: 10676343
    Abstract: A multi-layer sealing film for high seal yield is provided. In some embodiments, a substrate comprises a vent opening extending through the substrate, from an upper side of the substrate to a lower side of the substrate. The upper side of the substrate has a first pressure, and the lower side of the substrate has a second pressure different than the first pressure. The multi-layer sealing film covers and seals the vent opening to prevent the first pressure from equalizing with the second pressure through the vent opening. Further, the multi-layer sealing film comprises a pair of metal layers and a barrier layer sandwiched between metal layers. Also provided is a microelectromechanical systems (MEMS) package comprising the multilayer sealing film, and a method for manufacturing the multi-layer sealing film.
    Type: Grant
    Filed: November 28, 2018
    Date of Patent: June 9, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chih-Chien Yang, Ming-Lun Shih, Ren-Dou Lee, Jen-Hao Liu
  • Patent number: 10672913
    Abstract: A semiconductor device having a reduced amount of oxygen vacancy in a channel formation region of an oxide semiconductor is provided. Further, a semiconductor device which includes an oxide semiconductor and has improved electric characteristics is provided. Furthermore, a methods for manufacturing the semiconductor device is provided. An oxide semiconductor film is formed; a conductive film is formed over the oxide semiconductor film at the same time as forming a low-resistance region between the oxide semiconductor film and the conductive film; the conductive film is processed to form a source electrode and a drain electrode; and oxygen is added to the low-resistance region between the source electrode and the drain electrode, so that a channel formation region having a higher resistance than the low-resistance region is formed and a first low-resistance region and a second low-resistance region between which the channel formation region is positioned are formed.
    Type: Grant
    Filed: July 2, 2018
    Date of Patent: June 2, 2020
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Hideomi Suzawa, Tetsuhiro Tanaka, Hirokazu Watanabe, Yuhei Sato, Yasumasa Yamane, Daisuke Matsubayashi
  • Patent number: 10672848
    Abstract: A display device including a substrate, a source electrode and a drain electrode on the substrate, the source electrode and the drain electrode being spaced apart from each other, a first planarization layer on the source electrode and the drain electrode, a second planarization layer on the first planarization layer, and a first electrode on the second planarization layer. A step difference between a top of the first planarization layer and a top of the drain electrode is 100 ? or less.
    Type: Grant
    Filed: June 22, 2017
    Date of Patent: June 2, 2020
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Hyeon Bum Lee, Hyoeng Ki Kim, Kyong Heon Lee, Dong Ki Lee, Eon Joo Lee, Jin Whan Jung
  • Patent number: 10665690
    Abstract: A gate-controlled bipolar junction transistor includes a substrate, an emitter region, a base region disposed on one side of the emitter region, and a collector region disposed on one side of the base region and being opposite to the emitter region. The emitter region includes first fin structures, first metal gates extending across the first fin structures, and an emitter contact plug on the first fin structures. A gate contact region is disposed between the emitter region and the base region. Each of the first metal gates includes an extended contact end portion protruding toward the base region. The extended contact end portion is disposed within the gate contact region. A gate contact is disposed on the extended contact end portion.
    Type: Grant
    Filed: October 17, 2018
    Date of Patent: May 26, 2020
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chen-Wei Pan, Sheng Cho
  • Patent number: 10665512
    Abstract: Compressive and tensile stress is induced, respectively, on semiconductor fins in the pFET and nFET regions of a monolithic semiconductor structure including FinFETs. A tensile stressor is formed from dielectric material and a second, compressive stressor is formed from metal. The stressors may be formed in fin cut regions of the monolithic semiconductor structure and are configured to provide stress in the direction of FinFET current flow. The dielectric material may be deposited on the monolithic semiconductor structure and later removed from the fin cut regions of the pFET region. Metal exhibiting compressive residual stress is then deposited in the fin cut regions from which the dielectric material was removed. Gate cut regions may also be filled with the dielectric stressor material to impart substantially uniaxial tensile stress perpendicular to the semiconductor fins and perpendicular to electrical current flow.
    Type: Grant
    Filed: October 17, 2018
    Date of Patent: May 26, 2020
    Assignee: International Business Machines Corporation
    Inventors: Huimei Zhou, Kangguo Cheng, Michael P. Belyansky, Oleg Gluschenkov, Richard A. Conti, James Kelly, Balasubramanian Pranatharthiharan
  • Patent number: 10658508
    Abstract: Structures and formation methods of a semiconductor device structure are provided. The method includes forming a fin structure over a semiconductor substrate and forming a gate stack over the fin structure. The method also includes forming an epitaxial structure over the fin structure. The method further includes forming a dielectric layer over the epitaxial structure and forming an opening in the dielectric layer to expose the epitaxial structure. In addition, the method includes forming a modified region in the epitaxial structure. The modified region has lower crystallinity than an inner portion of the epitaxial structure and extends along an entirety of an exposed surface of the epitaxial structure. The method also includes forming a semiconductor-metal compound region on the epitaxial structure. All or some of the modified region is transformed into the semiconductor-metal compound region.
    Type: Grant
    Filed: July 18, 2018
    Date of Patent: May 19, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chia-Cheng Chen, Su-Hao Liu, Kuo-Ju Chen, Liang-Yin Chen
  • Patent number: 10658304
    Abstract: A semiconductor device includes an electroconductive shielding layer, an isolation layer formed with a frame-shaped opening, a wiring layer on the isolation layer to be surrounded by the opening, a semiconductor element on the wiring layer with its back surface facing the wiring layer, electroconductive pillars spaced apart from the semiconductor element and standing on the wiring layer, and an electroconductive frame standing on an exposed region of the shielding layer through the opening, with the frame surrounding the semiconductor element and the electroconductive pillars. The semiconductor device further includes an electrically insulating sealing resin that covers the wiring layer and the semiconductor element, and the frame is configured to be electrically connected to an external ground terminal.
    Type: Grant
    Filed: November 28, 2018
    Date of Patent: May 19, 2020
    Assignee: ROHM CO., LTD.
    Inventor: Hideaki Yanagida
  • Patent number: 10649496
    Abstract: A stretchable display device includes a substrate having a plurality of islands spaced apart from each other, and a plurality of bridges connecting each of the plurality of islands. A plurality of display units is disposed above the plurality of islands, respectively. A plurality of metal wirings are electrically connected to each of the plurality of display units. The plurality of metal wirings are disposed above the plurality of bridges. Each of the plurality of bridges includes a first region curved convexly in a first direction on a plane, and a second region curved concavely in the first direction. The second region is connected to the first region. Each of the plurality of metal wirings has a first width, and each of the plurality of bridges have a second width that is greater than the first width.
    Type: Grant
    Filed: May 2, 2019
    Date of Patent: May 12, 2020
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Jinwoo Choi, Youngse Jang, Haeyun Choi, Sungkook Park, Jaeik Lim
  • Patent number: 10643885
    Abstract: Methods of locally changing the BOX layer of a MOSFET device to a high-k layer to provide different Vts with one backside voltage and the resulting device are provided. Embodiments include providing a Si substrate having a BOX layer formed over the substrate and a SOI layer formed over the BOX layer; implanting a high current of dopants into at least one portion of the BOX layer; performing a high-temperature anneal of the BOX layer; forming first and second fully depleted silicon-on-insulator (FDSOI) transistors on the SOI layer, the first FDSOI transistors formed above either the BOX layer or the at least one portion of the BOX layer and the second FDSOI transistors formed above the at least one portion of the BOX layer; and applying a single voltage across a backside of the Si substrate.
    Type: Grant
    Filed: July 5, 2018
    Date of Patent: May 5, 2020
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Philipp Steinmann, Peter Javorka
  • Patent number: 10643995
    Abstract: A semiconductor device includes a plurality of active patterns protruding from a substrate, a gate structure intersecting the plurality of active patterns, a plurality of source/drain regions respectively on the plurality of active patterns at opposite sides of the gate structure, and source/drain contacts intersecting the plurality of active patterns, each of the source/drain contacts connected in common to the source/drain regions thereunder, each of the plurality of source/drain regions including a first portion in contact with a top surface of the active pattern thereunder, the first portion having a width substantially increasing as a distance from the substrate increases, and a second portion extending from the first portion, the second portion having a width substantially decreasing as a distance from the substrate increases, bottom surfaces of the source/drain contacts being lower than an interface between the first and second portions.
    Type: Grant
    Filed: April 10, 2019
    Date of Patent: May 5, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Changseop Yoon, Jayeol Goo, Sang Gil Kim
  • Patent number: 10636782
    Abstract: Circuits and methods for protecting a device are provided. A first device to be protected includes a gate dielectric of a first thickness. A second device includes a gate dielectric of a second thickness that is less than the first thickness. A gate is shared by the first device and the second device.
    Type: Grant
    Filed: November 16, 2018
    Date of Patent: April 28, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Kuo-Yu Chou, Shang-Fu Yeh, Yi-Ping Chao, Chih-Lin Lee
  • Patent number: 10636726
    Abstract: A semiconductor device includes an integrated circuit that is disposed at a first face side of a semiconductor substrate, the semiconductor substrate having a first face and a second face, the second face opposing the first face, the semiconductor substrate having a through hole from the first face to the second face; an external connection terminal that is disposed at the first face side; a conductive portion that is disposed in the through hole, the conductive portion being electrically connected to the external connection terminal; and an electronic element that is disposed at a second face side.
    Type: Grant
    Filed: September 12, 2019
    Date of Patent: April 28, 2020
    Assignee: Advanced Interconnect Systems Limited
    Inventors: Haruki Ito, Nobuaki Hashimoto
  • Patent number: 10636823
    Abstract: An image sensor assembly, a method of manufacturing the same, and a camera module are provided. The image sensor assembly includes an image sensor including a pixel region provided on a surface of the image sensor, a cover disposed above the pixel region, a spacer disposed on a surface of the cover and the spacer being configured to maintain a distance between the image sensor and the cover, and an adhesive configured to fixedly attach the spacer to the image sensor, wherein the spacer comprises a first and a second member disposed parallel to and at a distance from each other.
    Type: Grant
    Filed: January 29, 2018
    Date of Patent: April 28, 2020
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventors: Kang Hyun Lee, Sung Min Song, Jung Gon Choi, Heung Woo Park, Jae Hyun Lim