Patents Examined by Jonathan Han
  • Patent number: 10319763
    Abstract: A solid-state imaging apparatus includes: a solid-state imaging device photoelectrically converting light taken by a lens; and a light shielding member shielding part of light incident on the solid-state imaging device from the lens, wherein an angle made between an edge surface of the light shielding member and an optical axis direction of the lens is larger than an incident angle of light to be incident on an edge portion of the light shielding member.
    Type: Grant
    Filed: August 28, 2018
    Date of Patent: June 11, 2019
    Assignee: Sony Corporation
    Inventors: Toshiaki Iwafuchi, Masahiko Shimizu, Hirotaka Kobayashi
  • Patent number: 10319889
    Abstract: A light emitting device includes a light emitting element having a light emitting surface from which the light emitting element is configured to emit a first light having a first peak wavelength. A light transform layer is provided on the light emitting surface to transform the first light to a second light having a second peak wavelength longer than the first peak wavelength. A light-transmissive layer is provided on the light transform layer and includes a first surface that has a substantially flat shape and that is opposite to the light emitting surface and a second surface connected to the first surface and having a curved shape to surround the light emitting element. A reflecting film is provided between the light transform layer and the light-transmissive layer to extend along the first surface and the second surface so as to reflect the first light and to transmit the second light.
    Type: Grant
    Filed: December 6, 2017
    Date of Patent: June 11, 2019
    Assignee: NICHIA CORPORATION
    Inventors: Taiki Yuasa, Tomohisa Kishimoto
  • Patent number: 10319660
    Abstract: A heat transportation mechanism that is thermally conductive, but not electrically conductive, is provided so as to permit transportation of heat generated by a semiconductor device die to the exterior of a semiconductor device package. Embodiments can use a thermally conductive polymer structure, added to the package mold compound, to transport heat through the mold compound. The thermally conductive polymer structure can be fixed to the semiconductor device die prior to molding or can be included in an overmolding compound slug prior to performing the overmolding process. Flexibility of placement of the thermally conductive polymer structure is provided by using dielectric compounds.
    Type: Grant
    Filed: October 31, 2013
    Date of Patent: June 11, 2019
    Assignee: NXP USA, INC.
    Inventor: Christopher W. Argento
  • Patent number: 10315251
    Abstract: A high-precision three-dimensional laminated and shaped object is shaped based on a captured image. A three-dimensional laminating and shaping apparatus includes a material ejector that ejects a material of a three-dimensional laminated and shaped object onto a shaping table, a light beam irradiator that irradiates the ejected material with a light beam, an image capturer that captures a molten pool formed by irradiating the ejected material with the light beam, a scanning direction determiner that determines a scanning direction of the light beam with respect to a shaped object based on a change in a position of the shaping table, a detector that detects the molten pool based on an image captured by the image capturer and the scanning direction, and a shaping controller that controls at least one of an output of the light beam and a scanning speed of the light beam based on the detected molten pool.
    Type: Grant
    Filed: March 25, 2016
    Date of Patent: June 11, 2019
    Assignee: TECHNOLOGY RESEARCH ASSOCIATION FOR FUTURE ADDITIVE MANUFACTURING
    Inventor: Haruhiko Niitani
  • Patent number: 10307084
    Abstract: A person's fall risk may be determined based on machine learning algorithms. The fall risk information can be used to notify the person and/or a third party monitoring person (e.g. doctor, physical therapist, personal trainer, etc.) of the person's fall risk. This information may be used to monitor and track changes in fall risk that may be impacted by changes in health status, lifestyle behaviors or medical treatment. Furthermore, the fall risk classification may help individuals be more careful on the days they are more at risk for falling. The fall risk may be estimated using machine learning algorithms that process data from load sensors by computing basic and advanced punctuated equilibrium model (PEM) stability metrics.
    Type: Grant
    Filed: June 29, 2016
    Date of Patent: June 4, 2019
    Assignee: ZIBRIO INC.
    Inventors: Katharine Forth, Erez Lieberman Aiden
  • Patent number: 10312341
    Abstract: An integrated circuit device includes a first gate stack formed on a first high dielectric layer and comprising a first work function adjustment metal containing structure and a second gate stack formed on a second high dielectric layer and comprising a second work function adjustment metal containing structure having an oxygen content that is greater than that of the first work function adjustment metal containing structure.
    Type: Grant
    Filed: November 28, 2017
    Date of Patent: June 4, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Ha-jin Lim, Gi-gwan Park, Weon-hong Kim
  • Patent number: 10310560
    Abstract: A stretchable display device includes a substrate having a plurality of islands spaced apart from each other, and a plurality of bridges connecting each of the plurality of islands. A plurality of display units is disposed above the plurality of islands, respectively. A plurality of metal wirings are electrically connected to each of the plurality of display units. The plurality of metal wirings are disposed above the plurality of bridges. Each of the plurality of bridges includes a first region curved convexly in a first direction on a plane, and a second region curved concavely in the first direction. The second region is connected to the first region. Each of the plurality of metal wirings has a first width, and each of the plurality of bridges have a second width that is greater than the first width.
    Type: Grant
    Filed: August 11, 2017
    Date of Patent: June 4, 2019
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Jinwoo Choi, Youngse Jang, Haeyun Choi, Sungkook Park, Jaeik Lim
  • Patent number: 10312182
    Abstract: A semiconductor device includes an integrated circuit that is disposed at a first face side of a semiconductor substrate, the semiconductor substrate having a first face and a second face, the second face opposing the first face, the semiconductor substrate having a through hole from the first face to the second face; an external connection terminal that is disposed at the first face side; a conductive portion that is disposed in the through hole, the conductive portion being electrically connected to the external connection terminal; and an electronic element that is disposed at a second face side.
    Type: Grant
    Filed: October 8, 2018
    Date of Patent: June 4, 2019
    Assignee: ADVANCED INTERCONNECT SYSTEMS LIMITED
    Inventors: Haruki Ito, Nobuaki Hashimoto
  • Patent number: 10290834
    Abstract: An organic EL display device includes a pixel electrode, a pixel isolation insulating film on which an opening at a bottom of which the pixel electrode is exposed is formed, an aggregate of an organic material partially formed on the pixel electrode that is exposed at the bottom of the opening, an organic film, including a light emitting layer, that covers the pixel electrode and the aggregate, and an opposing electrode that covers the organic film. The aggregate is formed at a corner formed by the pixel electrode that is exposed at the bottom of the opening and an inner wall that forms the opening of the pixel isolation insulating film.
    Type: Grant
    Filed: March 7, 2017
    Date of Patent: May 14, 2019
    Assignee: Japan Display Inc.
    Inventor: Kaichi Fukuda
  • Patent number: 10290782
    Abstract: A method for mirror-coating lateral surfaces of optical components, a mirror-coated optical component and an optoelectronic semiconductor body mountable on surface are disclosed. In an embodiment, an optoelectronic semiconductor body includes a semiconductor chip having a radiation side and a contact side different from the radiation side, wherein contact elements for electrically contacting the semiconductor body are attached to the contact side, and wherein the contact elements are freely accessible. The body further includes a metal mirror layer disposed on the semiconductor chip, wherein the metal mirror layer has a reflectivity of at least 80% to radiation emitted by the semiconductor chip during operation, wherein the mirror layer is a continuous and contiguous mirror layer, which covers all sides of the semiconductor chip that are not the contact side and the radiation side by at least 95%, and wherein the mirror layer is arranged at the semiconductor chip in a form-fit manner.
    Type: Grant
    Filed: May 6, 2016
    Date of Patent: May 14, 2019
    Assignee: OSRAM Opto Semiconductors GmbH
    Inventors: Siegfried Herrmann, David O'Brien, David Racz
  • Patent number: 10287491
    Abstract: A coated phosphor comprises phosphor particles, wherein said phosphor particles comprise manganese-activated complex fluoride phosphors; and a coating on individual ones of said phosphor particles, said coating comprising a layer of carboxylic acid material encapsulating the individual phosphor particles.
    Type: Grant
    Filed: March 20, 2017
    Date of Patent: May 14, 2019
    Assignee: Intematix Corporation
    Inventor: Dejie Tao
  • Patent number: 10283502
    Abstract: A semiconductor device includes a plurality of active patterns protruding from a substrate, a gate structure intersecting the plurality of active patterns, a plurality of source/drain regions respectively on the plurality of active patterns at opposite sides of the gate structure, and source/drain contacts intersecting the plurality of active patterns, each of the source/drain contacts connected in common to the source/drain regions thereunder, each of the plurality of source/drain regions including a first portion in contact with a top surface of the active pattern thereunder, the first portion having a width substantially increasing as a distance from the substrate increases, and a second portion extending from the first portion, the second portion having a width substantially decreasing as a distance from the substrate increases, bottom surfaces of the source/drain contacts being lower than an interface between the first and second portions.
    Type: Grant
    Filed: October 4, 2017
    Date of Patent: May 7, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Changseop Yoon, Jayeol Goo, Sang Gil Kim
  • Patent number: 10283438
    Abstract: A semiconductor device includes an integrated circuit that is disposed at a first face side of a semiconductor substrate, the semiconductor substrate having a first face and a second face, the second face opposing the first face, the semiconductor substrate having a through hole from the first face to the second face; an external connection terminal that is disposed at the first face side; a conductive portion that is disposed in the through hole, the conductive portion being electrically connected to the external connection terminal; and an electronic element that is disposed at a second face side.
    Type: Grant
    Filed: June 22, 2018
    Date of Patent: May 7, 2019
    Assignee: ADVANCED INTERCONNECT SYSTEMS LIMITED
    Inventors: Haruki Ito, Nobuaki Hashimoto
  • Patent number: 10276565
    Abstract: A semiconductor device includes a substrate; a first device disposed on the substrate, and the first device includes at least two first gate stacks, in which the two adjacent first gate stacks have a first distance therebetween; a plurality of first gate spacers having a first thickness disposed on opposite sidewalls of the first gate stacks; the semiconductor device further includes a second device disposed on the substrate, and the second device includes at least two second gate stacks, in which the two adjacent second gate stacks have a second distance therebetween, and the first distance is smaller than the second distance; a plurality of second gate spacers having a second thickness disposed on opposite sidewalls of the second gate stacks, and the first thickness is greater than the second thickness.
    Type: Grant
    Filed: June 22, 2017
    Date of Patent: April 30, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chung-Pin Huang, Hou-Yu Chen, Chuan-Li Chen, Chih-Kuan Yu, Yao-Ling Huang
  • Patent number: 10276747
    Abstract: A substrate wafer composed of a hexagonal single crystal material including a C crystalline plane, an A crystalline plane, and an M-axis direction includes a top surface is a C-axis plane; a first side connecting to the aforementioned top surface and being substantially a curve line viewing from the direction perpendicular to the aforementioned C crystalline plane and including a curvature center; and a second side connecting to the aforementioned first side; and wherein there is a line segment defined by a shortest distance between the aforementioned second side and the aforementioned curvature center, and the aforementioned line segment is not parallel with the aforementioned M-axis direction.
    Type: Grant
    Filed: April 20, 2017
    Date of Patent: April 30, 2019
    Assignee: EPISTAR CORPORATION
    Inventors: Kai Shen Chen, Hsin Hsiung Huang, Wan Jung Lee, Pei Chia Chen, Yung Hsin Tai
  • Patent number: 10276705
    Abstract: A semiconductor structure having a buffer layer, a pseudomorphic, impurity doped, back-barrier layer disposed on the buffer layer, a channel layer disposed on the back-barrier layer, the channel layer lattice matched to the buffer layer, and a top barrier layer disposed on the channel layer. A Group III-Nitride transition layer is disposed between the buffer layer and the pseudomorphic back-barrier layer. The buffer layer and the pseudomorphic back-barrier layer are both Group III-Nitride materials. The Group III-Nitride material of the buffer layer is different from the Group III-Nitride material in the back-barrier layer. The back-barrier layer has a wider bandgap of than the buffer layer bandgap. The composition of the Group III-Nitride material in the transition layer varies from the composition of the Group III-Nitride material in the buffer layer to the composition of the Group III-Nitride material in the pseudomorphic back-barrier layer as a function of distance from the buffer layer.
    Type: Grant
    Filed: March 12, 2018
    Date of Patent: April 30, 2019
    Assignee: Raytheon Company
    Inventors: Brian D. Schultz, Eduardo M. Chumbes
  • Patent number: 10276498
    Abstract: In some embodiments, the present disclosure relates to an interconnect structure. The interconnect structure has a first dielectric layer disposed over a substrate and a conductive structure arranged within the first dielectric layer. An air-gap separates sidewalls of the conductive structure from the first dielectric layer. The air-gap continuously extends from a first side of the conductive structure to an opposing second side of the conductive structure.
    Type: Grant
    Filed: December 22, 2017
    Date of Patent: April 30, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Tai-I Yang, Cheng-Chi Chuang, Yung-Chih Wang, Tien-Lu Lin
  • Patent number: 10276568
    Abstract: In a method for manufacturing a semiconductor device, a doped layer doped with a first dopant is formed in a substrate. A semiconductor layer is formed on the doped layer. A fin structure is formed by patterning at least the semiconductor layer and the doped layer such that the fin structure comprises a channel region including the semiconductor layer, and a well region including the doped layer. An isolation insulating layer is formed such that the channel region of the fin structure protrudes from the isolation insulating layer and the well region of the fin structure is embedded in the isolation insulating layer. A gate structure is formed over a part of the fin structure and the isolation insulating layer. The semiconductor layer is at least one of a doped silicon layer or a non-doped silicon layer.
    Type: Grant
    Filed: February 27, 2018
    Date of Patent: April 30, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yu-Sheng Wu, Chen Hua Tsai, Hou-Yu Chen, Chia-Wei Soong, Chih-Pin Tsao
  • Patent number: 10269807
    Abstract: A semiconductor arrangement includes an active region including a semiconductor device. The semiconductor arrangement includes a capacitor having a first electrode layer, a second electrode layer, and an insulating layer between the first electrode layer and the second electrode layer. At least three dielectric layers are between a bottom surface of the capacitor and the active region.
    Type: Grant
    Filed: December 4, 2017
    Date of Patent: April 23, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Chern-Yow Hsu, Chen-Jong Wang, Chia-Shiung Tsai, Shih-Chang Liu, Xiaomeng Chen
  • Patent number: 10268749
    Abstract: An approximate data structure to represent clusters of observation records of a data set is identified. A hierarchical representation of a plurality of clusters, including the targeted number of clusters among which the observation records are to be distributed, is generated. Each node of the hierarchy comprises an instance of the approximate data structure. Until a set of termination criteria are met, iterations of a selected clustering methodology are run. In a given iteration, distances of observation records from the cluster representatives of a current version of the model are computed using the hierarchical representation, and a new version of the model with modified cluster representatives is generated.
    Type: Grant
    Filed: January 7, 2016
    Date of Patent: April 23, 2019
    Assignee: Amazon Technologies, Inc.
    Inventors: Gourav Roy, Amit Chandak, Prateek Gupta, Srujana Merugu, Aswin Natarajan, Sathish Kumar Palanisamy, Gowda Dayananda Anjaneyapura Range, Jagannathan Srinivasan, Bharath Venkatesh