Abstract: A microelectronic device comprising tiers of alternating dielectric materials and conductive materials, pillars extending through the tiers, and a doped dielectric material adjacent to the tiers. The doped dielectric material comprises a heterogeneous chemical composition comprising one or more dopants. Conductive contact structures are in the doped dielectric material. Additional microelectronic devices, microelectronic systems, and methods of forming microelectronic devices are disclosed.

Abstract: A package includes a mounting plate having a first part able to dissipate heat and a second part able to transmit and/or receive electrical signals. A cladding houses a first electronic chip and second electronic chip. The first electronic chip has a first semiconductor substrate (giving off, in operation, a first quantity of heat) mounted to the first part of the mounting plate and electrically connected by wires to the second part of the mounting plate. The second electronic chip has a second semiconductor substrate (giving off, in operation, a second quantity of heat) mounted to an interposer support including an interconnection network. An array of connection balls interconnects the interposer support to the first part of the mounting plate and the second part of the mounting plate. The first and second semiconductor substrates are different.

Abstract: A method of preparing a quantum dot, an optical member including the quantum dot prepared using the method, and an electronic device including the quantum dot are provided. The method includes forming a first particle including a core and a protective shell from a quantum dot composition including a precursor containing a tellurium (Te) element, a precursor containing a Group II element, and a precursor containing a Group VI element; purifying the first particle; and forming a second particle including a first shell by mixing the first particle with a first shell composition including the precursor containing a Group II element and the precursor containing a Group VI element and forming the first shell from the protective shell.

Abstract: The present disclosure relates to a photodetection device and an electronic apparatus that allow for reducing surface reflection from an on-chip microlens and suppressing deterioration of image quality. Provided is a photodetection device including: a plurality of pixels that have photoelectric conversion units; on-chip microlenses that are formed in such a way as to correspond to the individual pixels; and an antireflection film that is formed on a surface of the on-chip microlens, in which the antireflection film is constituted by a stacking of: a first inorganic film that is formed by a metal oxide film; and a second inorganic film that is formed on a surface of the first inorganic film and has a lower refractive index than the first inorganic film. The present disclosure can be applied to, for example, a CMOS solid-state imaging device.

Abstract: A semiconductor package includes: a carrier having a first side and an opposing second side; a semiconductor die arranged on the first side of the carrier; a heat conductor part arranged on the second side of the carrier; an encapsulation body encapsulating the semiconductor die, wherein the heat conductor part is exposed from the encapsulation body, and wherein the heat conductor part has a different material composition than the encapsulation body; and a scratch protection layer covering the heat conductor part, wherein the scratch protection layer has a hardness which is at least five times higher than a hardness of the heat conductor part.

Abstract: This application discloses a unit structure of a silicon photomultiplier tube, including a first conductive type heavily doped first electrode region located on a first side of the shallow trench isolation, a second conductive type heavily doped second electrode region located on a second side, and a quenching resistor located on a top surface of the shallow trench isolation. A photosensitive layer is formed in the silicon substrate at bottoms of the first electrode region, the shallow trench isolation and the second electrode region. The first electrode region, the photosensitive layer and the second electrode region form a Geiger mode avalanche photodiode. A first end of the quenching resistor is connected to the first electrode region through a first metal interconnect structure. A second end of the quenching resistor is connected to a first electrode. The second electrode region is connected to a second electrode.

Abstract: A phosphor powder including phosphor particles of a phosphor represented by a general formula Mx(Si, Al)2(N, O)3±y and in which a part of M is substituted with a Ce element, the phosphor powder includes phosphor particles in which a Si/Al atomic ratio is equal to or more than 1.5 and equal to or less than 6, an O/N atomic ratio is equal to or more than 0 and equal to or less than 0.1, 5 to 50 mol % of M is Li, and 0.5 to 10 mol % of M is Ce. In a case where a volume-based cumulative 10% particle size, a volume-based cumulative 50% particle size, and a volume-based cumulative 90% particle size of this phosphor powder measured by a laser diffraction scattering method are defined as D10, D50, and D90, respectively, (D90?D10)/D50 is equal to or more than 0.7 and equal to or less than 1.1.

Abstract: A semiconductor device having simplicity in design and improved performance and methods for fabricating the same are provided. The semiconductor device includes a substrate including a frontside and a backside opposite the frontside, an electronic device on the frontside of the substrate, an interlayer insulating layer covering the electronic device, a frontside wiring structure on the interlayer insulating layer, a backside wiring structure on the backside of the substrate, and at least one unit chain connecting the electronic device with the backside wiring structure, the unit chain including a through plug passing through the substrate, a connection contact on the interlayer insulating layer, a first chain plug passing through the interlayer insulating layer to connect the through plug with the connection contact, and a second chain plug passing through the interlayer insulating layer to be connected to the through plug.

Abstract: A semiconductor memory device includes a bit line on a substrate and extending in a first direction parallel to a top surface of the substrate, a channel pattern connected to a top surface of the bit line and extending in a second direction perpendicular to the top surface of the substrate, a first drain pattern on the channel pattern, a first word line adjacent to a lower portion of the first drain pattern and the channel pattern, and a gate insulating layer between the lower portion of the first drain pattern and the first word line and between the channel pattern and the first word line. An energy band gap of a first material of the first drain pattern is greater than an energy band gap of a second material of the channel pattern.

Abstract: A display device includes a display panel, and a color conversion member disposed on the display panel. The color conversion member includes a plurality of partition walls disposed on the display panel and spaced apart from each other, and a color control part disposed between the plurality of partition walls. Each of the plurality of partition walls includes a first sub partition wall including a scattering body, and a second sub partition wall disposed on the first sub partition wall, and including a liquid repellent. The second sub partition wall has a higher light transmittance than the first sub partition wall.

Abstract: Memory cells, semiconductor devices, semiconductor stacked structures, and fabrication methods are provided. An example memory cell includes a capacitor and a transistor stacked over the capacitor in a compact configuration. The capacitor includes a floating gate, a high-k dielectric layer, and a metal gate. The metal gate extends horizontally from a first sidewall to a second sidewall and vertically from a bottom surface to a top surface. The transistor includes the metal gate and a gate dielectric layer disposed on the metal gate. The gate dielectric layer includes two side portions respectively disposed on the two sidewalls of the metal gate and, and a top portion disposed on the top surface of the metal gate. The transistor further includes two separate S/D regions respectively formed on the two side portions of the gate dielectric layer, and a channel region formed on the top portion of the gate dielectric layer.

Abstract: An image sensor includes an image sensor die, a light transmitting element, at least one anti-reflection coating and at least one anti-reflection structure. The image sensor die includes a photoelectric conversion layer and a micro lens layer. The micro lens layer is disposed above the photoelectric conversion layer for converging the light onto the photoelectric conversion layer. The light transmitting element is disposed above the micro lens layer, and a gap is formed between the light transmitting element and the micro lens layer, the light passes through the light transmitting element and then travels into the image sensor. The anti-reflection coating is at least disposed on an upper surface of the light transmitting element. The anti-reflection structure is disposed on at least one of a lower surface of the light transmitting element and the micro lens layer.

Abstract: A light emitting display device includes a first display area; and a second display area disposed adjacent to the first display area, wherein the second display area includes a pixel driving part, a main light-emitting element directly connected to the pixel driving part, and an additional light-emitting element connected to the main light-emitting element, the additional light-emitting element overlaps a peripheral driving part in a plan view, the peripheral driving part generates a signal provided to the pixel driving part, the main light-emitting element and the additional light-emitting element each include a first electrode, an emission layer, and a second electrode, the pixel driving part is electrically connected to the second electrode of the main light-emitting element and the second electrode of the additional light-emitting element, and the second electrode of the additional light-emitting element and the second electrode of the main light-emitting element are separated by a separator.

Abstract: A semiconductor device includes a lower structure; a vertical conductive line extending in a first direction which is perpendicular to a surface of the lower structure; a reservoir capacitor disposed over the lower structure to be spaced apart from the vertical conductive line; a bridge horizontal layer disposed between the vertical conductive line and the reservoir capacitor and extending horizontally in a second direction which is parallel to the surface of the lower structure; and a pair of horizontal layers extending in a third direction intersecting the bridge horizontal layer with the bridge horizontal layer interposed therebetween.

Abstract: A light-emitting device includes a base member, a frame member and a light-emitting element. The frame member is fixed to the base member and has one or more inner lateral surfaces and one or more outer lateral surfaces. The frame member includes a first part containing a wavelength conversion material and defining one part of the one or more inner lateral surfaces and one part of the one or more outer lateral surfaces, and a second part connected with the first part and defining another part of the one or more inner lateral surfaces and another part of the one or more outer lateral surfaces. The light emitting element has a light-emitting surface, and is configured to emit, from the light-emitting surface, light to be incident on the one part of the one or more inner lateral surfaces defined by the first part of the frame member.

Abstract: An integrated circuit structure includes a device layer including an upper device above a lower device. The upper device includes an upper source or drain region, and an upper source or drain contact coupled to the upper source or drain region. The lower device includes a lower source or drain region. A first conductive feature is below the device layer, where the first conductive feature is coupled to the lower source or drain region. A second conductive feature vertically extends through the device layer. In an example, the second conductive feature is to couple (i) the first conductive feature below the device layer and (ii) an interconnect structure above the device layer. Thus, the first and second conductive features facilitate a connection between the interconnect structure on the frontside of the integrated circuit and the lower source or drain region towards the backside of the integrated circuit.

Abstract: Structures having raised epitaxy on channel structure transistors are described. In an example, an integrated circuit structure includes a channel structure having multi-layer epitaxial source or drain structures thereon, the multi-layer epitaxial source or drain structures having a recess extending there through. A gate dielectric layer is on a bottom and along sides of the recess and laterally surrounded by the epitaxial source or drain structures. A gate electrode is on and laterally surrounded by the gate dielectric layer. The gate electrode has an uppermost surface below an uppermost surface of the gate dielectric layer.

Abstract: According to embodiments, a light emitting display device includes a light emitting diode (LED) positioned on a substrate and including an emission layer, a pixel definition layer including an opening corresponding to the emission layer, and a plurality of light-shielding linear patterns positioned on the pixel definition layer and the emission layer and extending in a first direction. The plurality of light-shielding linear patterns include a recess portion of a concave shape.

Abstract: An integrated circuit device includes a first-type active-region semiconductor structure extending and a second-type active-region semiconductor structure both extending in a first direction. The second-type active-region semiconductor structure is stacked with the first-type active-region semiconductor structure. The integrated circuit device also includes a front-side conductive layer above the two active-region semiconductor structures and a back-side conductive layer below the two active-region semiconductor structures. The integrated circuit device still includes a front-side power rail extending in the second direction in the front-side conductive layer and a back-side power rail extending in the second direction in the back-side conductive layer. The integrated circuit device further includes a first source conductive segment connected to the front-side power rail and a second source conductive segment connected to the back-side power rail.

Abstract: An integrated circuit (IC) structure includes a gate structure, source/drain epitaxial structures, a front-side interconnection structure, a backside dielectric layer, and a backside via. The source/drain epitaxial structures are respectively on opposite sides of the gate structure. The front-side interconnection structure is on front-sides of the source/drain epitaxial structures. The backside dielectric layer is on backsides of the source/drain epitaxial structures. The backside via extends through the backside dielectric layer to one of the source/drain epitaxial structures, and has a maximal lateral dimension larger than a lateral dimension of the source/drain epitaxial structure.