Patents Examined by Jonathan Han
  • Patent number: 11961947
    Abstract: Disclosed herein is a transfer substrate used for manufacturing a display device using a light emitting semiconductor device. The transfer substrate include a base substrate, and a divided unit phosphor structure arranged on the base substrate and transferred onto the light emitting semiconductor device.
    Type: Grant
    Filed: June 16, 2021
    Date of Patent: April 16, 2024
    Assignee: LG ELECTRONICS INC.
    Inventor: Hwanjoon Choi
  • Patent number: 11955541
    Abstract: A semiconductor device includes a substrate, a buffer layer disposed on the substrate, a channel layer disposed on the buffer layer, a barrier layer disposed on the buffer layer, and a passivation layer disposed on the barrier layer. The semiconductor device further includes a device isolation region that extends through the passivation layer, the barrier layer, and at least a portion of the channel layer, and encloses a first device region of the semiconductor device. A damage concentration of the device isolation region varies along a depth direction, and is highest near a junction between the barrier layer and the channel layer.
    Type: Grant
    Filed: May 31, 2021
    Date of Patent: April 9, 2024
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chi-Hsiao Chen, Kai-Lin Lee
  • Patent number: 11949030
    Abstract: Various embodiments of the present disclosure are directed towards an image sensor with a passivation layer for dark current reduction. A device layer overlies a substrate. Further, a cap layer overlies the device layer. The cap and device layers and the substrate are semiconductor materials, and the device layer has a smaller bandgap than the cap layer and the substrate. For example, the cap layer and the substrate may be silicon, whereas the device layer may be or comprise germanium. A photodetector is in the device and cap layers, and the passivation layer overlies the cap layer. The passivation layer comprises a high k dielectric material and induces formation of a dipole moment along a top surface of the cap layer.
    Type: Grant
    Filed: March 10, 2021
    Date of Patent: April 2, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Hao Chiang, Eugene I-Chun Chen, Chih-Ming Chen
  • Patent number: 11948950
    Abstract: An image acquisition device includes an array of color filters and an array of microlenses over the array of color filters. At least one layer made from an inorganic dielectric material is formed between the array of color filters and the array of microlenses.
    Type: Grant
    Filed: April 7, 2021
    Date of Patent: April 2, 2024
    Assignee: STMicroelectronics (Crolles 2) SAS
    Inventors: Mickael Fourel, Laurent-Luc Chapelon
  • Patent number: 11942551
    Abstract: A semiconductor device includes a multi-channel active pattern, a plurality of gate structures on the multi-channel active pattern and spaced apart from each other in a first direction, the plurality of gate structures including a gate electrode that extends in a second direction different from the first direction, a source/drain recess between the adjacent gate structures, and a source/drain pattern on the multi-channel active pattern in the source/drain recess, wherein the source/drain pattern includes: a semiconductor liner layer including silicon-germanium and extending along the source/drain recess, a semiconductor filling layer including silicon-germanium on the semiconductor liner layer, and at least one or more semiconductor insertion layers between the semiconductor liner layer and the semiconductor filling layer, and wherein the at least one or more semiconductor insertion layers have a saddle structure.
    Type: Grant
    Filed: November 5, 2021
    Date of Patent: March 26, 2024
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jung Taek Kim, Seok Hoon Kim, Pan Kwi Park, Moon Seung Yang, Seo Jin Jeong, Min-Hee Choi, Ryong Ha
  • Patent number: 11942496
    Abstract: A digital image sensor package includes an image sensor substrate and a glass covering. The image sensor substrate carries photodiodes. The glass covering has a bottom surface, a top surface opposite the bottom surface, and a sidewall delimiting a perimeter edge of the glass covering. The glass covering overlies the photodiodes. A surface area of the top surface of the glass covering is greater than a surface area of the bottom surface of the glass covering such that the sidewall is anti-perpendicular to the top and bottom surfaces of the glass.
    Type: Grant
    Filed: May 21, 2021
    Date of Patent: March 26, 2024
    Assignee: STMicroelectronics Pte Ltd
    Inventors: Laurent Herard, David Gani
  • Patent number: 11943523
    Abstract: An image sensor device includes an image sensor, a substrate including first and second pads spaced apart from each other, a first support member on which an optical filter is mounted, a second support member further adjacent to an outer edge of the substrate than the first support member, and an optical device on the optical filter and the image sensor, wherein the image sensor is electrically connected to the first pad, and wherein at least one of the first or second support members is electrically connected to the second pad.
    Type: Grant
    Filed: July 29, 2021
    Date of Patent: March 26, 2024
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Insang Song, Hyunjin Kang, Seunghak Lee
  • Patent number: 11935966
    Abstract: A transistor device includes a first source/drain region and a second source/drain region spaced apart from each other; a channel layer electrically connected to the first and second source/drain regions; a gate insulator layer; a gate electrode isolated from the channel layer by the gate insulator layer; and a UV-attenuating layer disposed on the channel layer to protect the channel layer from characteristic degradation caused by UV light.
    Type: Grant
    Filed: April 28, 2021
    Date of Patent: March 19, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Katherine H. Chiang, Neil Quinn Murray, Ming-Yen Chuang, Chung-Te Lin
  • Patent number: 11937445
    Abstract: A display panel and a display device, the display panel includes an encapsulation cover plate and a glass substrate, a light emitting unit and a driving circuit layer are arranged between the encapsulation cover plate and the glass substrate, a conductive layer and an encapsulation material layer are overlaid and arranged between the encapsulation region of the encapsulation cover plate and the glass substrate, the conductive layer is provided with a plurality of openings arranged at intervals, and an orthographic projection of the opening on the encapsulation material layer is separated from a midline between an inner edge and an outer edge of the encapsulation material layer.
    Type: Grant
    Filed: May 25, 2021
    Date of Patent: March 19, 2024
    Assignee: KunShan Go-Visionox Opto-Electronics Co., Ltd
    Inventor: Yanqin Song
  • Patent number: 11935909
    Abstract: An electronic device includes a first module and a second module stacked upon the first module in a stacking direction. The first module includes a pixel substrate and a counter substrate disposed opposite to each other. The pixel substrate is defined with a plurality of pixels. The second module is disposed at one side of the first module adjacent to the counter substrate and away from the pixel substrate. The second module includes a plurality of micro-photoelectric units and a protection layer. The protection layer stacks upon the micro-photoelectric units and is disposed at one side of the second module away from the first module. Each of the micro-photoelectric units unshields one or more of the pixels in the stacking direction. Each micro-photoelectric unit includes a micro-photoelectric element, and at least one of the micro-photoelectric elements is a sensor element.
    Type: Grant
    Filed: January 7, 2021
    Date of Patent: March 19, 2024
    Assignee: LG DISPLAY CO., LTD.
    Inventor: Hsien-Te Chen
  • Patent number: 11929439
    Abstract: A transistor in an embodiment includes an oxide semiconductor layer on a substrate, the oxide semiconductor layer including a first region and a second region, a first gate electrode including a region overlapping the oxide semiconductor layer, the first gate electrode being arranged on a surface of the oxide semiconductor layer opposite to the substrate, a first insulating layer between the first gate electrode and the oxide semiconductor layer, and a first oxide conductive layer and a second oxide conductive layer between the oxide semiconductor layer and the substrate, the first oxide conductive layer and the second oxide conductive layer each including a region in contact with the oxide semiconductor layer.
    Type: Grant
    Filed: January 11, 2022
    Date of Patent: March 12, 2024
    Assignee: MIKUNI ELECTRON CORPORATION
    Inventor: Sakae Tanaka
  • Patent number: 11923420
    Abstract: A semiconductor device according to an embodiment includes: a silicon carbide layer; a metal layer; and a conductive layer positioned between the silicon carbide layer and the metal layer, the conductive layer containing a silicide of one metal element (M) selected from the group consisting of nickel (Ni), palladium (Pd), and platinum (Pt), and the conductive layer having a carbon concentration of 1×1017 cm?3 or less.
    Type: Grant
    Filed: January 20, 2023
    Date of Patent: March 5, 2024
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventor: Tatsuo Shimizu
  • Patent number: 11923358
    Abstract: A device comprises a first transistor, a second transistor, a first contact, and a second contact. The first transistor comprises a first gate structure, first source/drain regions on opposite sides of the first gate structure, and first gate spacers spacing the first gate structure apart from the first source/drain regions. The second transistor comprises a second gate structure, second source/drain regions on opposite sides of the second gate structure, and second gate spacers spacing the second gate structure apart from the second source/drain regions. The first contact forms a first contact interface with one of the first source/drain regions. The second contact forms a second contact interface with one of the second source/drain regions. An area ratio of the first contact interface to top surface the first source/drain region is greater than an area ratio of the second contact interface to top surface of the second source/drain region.
    Type: Grant
    Filed: July 28, 2022
    Date of Patent: March 5, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chung-Pin Huang, Hou-Yu Chen, Chuan-Li Chen, Chih-Kuan Yu, Yao-Ling Huang
  • Patent number: 11923476
    Abstract: A method of manufacturing a display device includes forming a first light-emitting area on a substrate, and forming a first color adjustment pattern on the first light-emitting area by emitting first light from the first light-emitting area, wherein the first light-emitting area includes a first semiconductor layer, a second semiconductor layer provided on the first semiconductor layer, a first active layer arranged between the first semiconductor layer and the second semiconductor layer, a first contact electrically connecting the substrate and the first semiconductor layer, and a first preliminary common electrode electrically connected to the second semiconductor layer.
    Type: Grant
    Filed: October 17, 2022
    Date of Patent: March 5, 2024
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Nakhyun Kim, Junhee Choi, Kiho Kong, Deukseok Chung
  • Patent number: 11921392
    Abstract: According to one embodiment, a semiconductor device includes an insulating substrate, a first metal layer on the insulating substrate, a first insulating layer on the insulating substrate and the first metal layer, a semiconductor layer on the first insulating layer, a second insulating layer on the semiconductor layer and the first insulating layer, a second metal layer on the second insulating layer, and a first electrode and a second electrode which are electrically connected to the semiconductor layer. The first metal layer overlaps the second metal layer. A third metal layer contacts a top surface of the second metal layer and a top surface of the first metal layer.
    Type: Grant
    Filed: September 15, 2022
    Date of Patent: March 5, 2024
    Assignee: Japan Display Inc.
    Inventors: Yohei Yamaguchi, Arichika Ishida, Hidekazu Miyake, Hiroto Miyake, Isao Suzumura
  • Patent number: 11923361
    Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a semiconductor fin over a substrate and multiple semiconductor nanostructures suspended over the semiconductor fin. The semiconductor device structure also includes a gate stack extending across the semiconductor fin, and the gate stack wraps around each of the semiconductor nanostructures. The semiconductor device structure further includes a first epitaxial structure and a second epitaxial structure sandwiching the semiconductor nanostructures. In addition, the semiconductor device structure includes an isolation structure between the semiconductor fin and the gate stack. The isolation structure extends exceeding opposite sidewalls of the first epitaxial structure.
    Type: Grant
    Filed: July 5, 2022
    Date of Patent: March 5, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Shi-Ning Ju, Kuo-Cheng Chiang, Kuan-Lun Cheng, Chih-Hao Wang
  • Patent number: 11916024
    Abstract: A method of forming a semiconductor device comprising forming a patterned resist over a stack comprising at least one material and removing a portion of the stack exposed through the patterned resist to form a stack opening. A portion of the patterned resist is laterally removed to form a trimmed resist and an additional portion of the stack exposed through the trimmed resist is removed to form steps in sidewalls of the stack. A dielectric material is formed between the sidewalls of the stack to substantially completely fill the stack opening, and the dielectric material is planarized. Additional methods are disclosed, as well as semiconductor devices.
    Type: Grant
    Filed: September 14, 2021
    Date of Patent: February 27, 2024
    Assignee: Micron Technology, Inc.
    Inventors: Rohit Kothari, Adam L Olson, John D. Hopkins, Jeslin J. Wu
  • Patent number: 11916118
    Abstract: A device is disclosed. The device includes a first epitaxial region, a second epitaxial region, a first gate region between the first epitaxial region and a second epitaxial region, a first dielectric structure underneath the first epitaxial region, a second dielectric structure underneath the second epitaxial region, a third epitaxial region underneath the first epitaxial region, a fourth epitaxial region underneath the second epitaxial region, and a second gate region between the third epitaxial region and a fourth epitaxial region and below the first gate region. The device also includes, a conductor via extending from the first epitaxial region, through the first dielectric structure and the third epitaxial region, the conductor via narrower at an end of the conductor via that contacts the first epitaxial region than at an opposite end.
    Type: Grant
    Filed: April 4, 2023
    Date of Patent: February 27, 2024
    Assignee: Intel Corporation
    Inventors: Ehren Mannebach, Aaron Lilak, Hui Jae Yoo, Patrick Morrow, Anh Phan, Willy Rachmady, Cheng-Ying Huang, Gilbert Dewey
  • Patent number: 11916175
    Abstract: A light emitting device includes a semiconductor light emitting element which emits excitation light having a peak wavelength in a range of 440 to 450 nm and a fluorescent body layer which is provided on the semiconductor light emitting element, is excited by the excitation light from the semiconductor light emitting element, and contains a first fluorescent body and a second fluorescent body which emit first fluorescent light and second fluorescent light. The first fluorescent light has a peak wavelength in a range of 540 to 575 nm, and the second fluorescent light has a peak wavelength in a range of 590 to 605 nm. In mixed color light of the radiation light, the intensity of the radiation light of the semiconductor light emitting element is 1/10 to 1/60 of the intensity of the combined light of the radiation light from the first fluorescent body and the second fluorescent body.
    Type: Grant
    Filed: March 2, 2020
    Date of Patent: February 27, 2024
    Assignee: STANLEY ELECTRIC CO., LTD.
    Inventors: Masaki Odawara, Kenji Ikeda, Shotaro Nishiki, Tsuzumi Higashiyama, Kazuhisa Shinno
  • Patent number: 11916163
    Abstract: A system and method are provided for repairing an emissive element display. If a defective emissive element is detected in a subpixel, a subpixel repair interface isolates the defective emissive element. The repair interface may be a parallel repair interface with n number of selectively fusible electrically conductive repair nodes, connected in parallel to a control line of the matrix. Alternatively, the repair interface may be a series repair interface with m number of repair nodes, selectively connectable to bypass adjacent (defective) series-connected emissive elements. If the subpixel emissive elements are connected in parallel, and a defective low impedance emissive element is detected, a parallel repair interface fuses open a connection between the defective emissive element and a matrix control line. If the subpixels include series-connected emissive elements, and a high impedance emissive element is detected, a series repair interface forms a connection bypassing the defective emissive element.
    Type: Grant
    Filed: September 2, 2021
    Date of Patent: February 27, 2024
    Assignee: eLux, Inc.
    Inventors: Jong-Jan Lee, Paul J. Schuele