Abstract: Disclosed herein are techniques for micro-light emitting diodes (micro-LEDs). According to certain embodiments, a micro-LED device includes a micro-LED comprising a semiconductor mesa structure configured to emit light, a spacer layer on the micro-LED, and a micro-lens on the spacer layer and configured to extract and collimate the light emitted by the micro-LED, where a thickness of the spacer layer is selected such that a focal point of the micro-lens is at a front surface of the semiconductor mesa structure.

Abstract: An electronic device and a manufacturing method thereof are disclosed. The electronic device includes a substrate, an electronic element, a barrier layer, a light absorbing layer, and a filter layer. The electronic element is disposed on the substrate. The barrier layer is disposed on the substrate and surrounds a side surface of the electronic element. The light absorbing layer is disposed on the barrier layer. The filter layer is disposed on the electronic element.

Abstract: An integrated circuit (IC) device is described. The IC device includes a semiconductor-on-insulator (SOI) substrate having a first-type diffusion region. The IC device also includes a first, first-type transistor on the first-type diffusion region. The IC device further includes a second, first-type transistor on the first-type diffusion region. The IC device also includes a first, second-type implant region. The first, second-type implant region includes a gate overlap region partially overlapped with a gate region of the second, first-type transistor to provide a body contact of the second, first-type transistor and to couple a source region of the second, first-type transistor to a drain region of the first, first-type transistor in series.

Abstract: A method of forming a semiconductor structure includes providing a substrate with an array region, a peripheral region, and a transition region between the array region and the peripheral region. A patterned floating gate layer is formed on the array region and the peripheral region, and a stacked layer is conformally formed on the substrate, wherein a recess is formed over the transition region. A photoresist layer is formed on the substrate, and the photoresist layer is patterned to form an array region pattern on the stacked layer of the array region, wherein a portion of the photoresist layer remains at the bottom of the recess, and a recess pattern is formed. The array region pattern and the recess pattern are sequentially transferred to the stacked layer, the patterned floating gate layer and the substrate to form a plurality of arrays and a pair of blocking structures.

Abstract: Provided are a color conversion structure, a display apparatus, and a method of manufacturing a color conversion structure. The color conversion structure includes a bank structure including a groove, a color conversion layer accommodated in the groove, and a cover layer provided on the color conversion layer.

Abstract: A package includes a mounting surface on which an electronic component is to be mounted, a cavity, and an attachment surface to which a lid is to be attached through an adhesive layer. The package includes: a bottom containing ceramics and having the mounting surface; and a frame containing ceramics and having the attachment surface. The attachment surface of the frame includes an inner end adjacent to the cavity and an outer end opposite to the inner end in at least one cross-sectional view spanning an inside and an outside of the cavity, the attachment surface having a protruding shape protruding in a thickness direction. At least one of the inner end or the outer end is made lower than a most protruding portion of the protruding shape by 10 ?m or more.

Abstract: Provided is an electronic device including: a biometric information sensing layer including a sensor; an optical pattern layer disposed on the biometric information sensing layer, and including a plurality of transmission parts and a light shielding part; and a display layer disposed on the optical pattern layer. When a fill factor (FF) of the sensor, which is a ratio of the amount of light received by the sensor to the total amount of light incident onto the sensor, is about 10% to about 70%, a field of view (FOV) of light incident onto the sensor is about 15° to about 30°.

Abstract: A texture recognition module and a display device, the texture recognition module includes a texture recognition substrate including a texture acquisition region and a peripheral region at least partially surrounding the texture acquisition region, and the texture recognition substrate includes a base substrate, multiple photosensitive sub-pixels, an optical module layer and a support layer, the multiple photosensitive sub-pixels are arranged on the base substrate and located in the texture acquisition region, each photosensitive sub-pixel includes a photosensitive element and for texture acquisition, the optical module layer is arranged on a side of the multiple photosensitive sub-pixels away from the base substrate and configured to adjust light transmission, and the support layer is arranged on a side of the optical module layer away from the base substrate and includes an acquisition opening which exposes the multiple photosensitive sub-pixels. The texture recognition module has a better stability.

Abstract: An image sensor includes a first color filter disposed on a first photodiode, a first grid, and a first micro lens disposed on the first color filter and the first grid. The first grid includes a first main portion and a first shielding portion extended from the first main portion. The first main portion surrounds the first color filter and the first shielding portion partially covers the first color filter such that a first cavity defined by the first shielding portion is configured over the first color filter. The first color filter or the first micro lens includes a first protruding portion filled in the first cavity, and a width of the first protruding portion is in a range from 0.1 pixel size to 0.8 pixel size. A manufacturing method of an image sensor is also disclosed.

Abstract: The present invention provides a reduced-height image-capturing module, which includes a lens assembly, an image-sensing chip, a carrier base and a circuit substrate. The carrier base has a base body, two extending plate bodies extending and a base groove recessed. A lower portion of the base body enters a through opening of the circuit substrate, and the two extending plate bodies cross over the through opening of the circuit substrate and are disposed on an upper surface of the circuit substrate. The image-sensing chip is disposed on a recessed bottom surface of the base groove which is not at the same level as the upper surface of the circuit substrate, so that the recessed bottom surface is lower than the upper surface of the circuit substrate. The lens assembly is disposed on the upper portion of the base body and corresponds to the image-sensing chip.

Abstract: A backlight module and a display device are disclosed. The backlight module includes a light board and a heat dissipation structure. Multiple light-emitting elements are arranged in a matrix on the light board. The heat dissipation structure includes a first control layer arranged on a side of the light board facing away from the light-emitting elements, and a second control layer opposite to the first control layer. There is a gap between the first control layer and second control layer, and there is disposed a coolant droplet in the gap. When a light-emitting element satisfies a first heating condition, the first control layer and second control layer control a coolant droplet to move to a position underneath the light-emitting element. When the light-emitting element satisfies a second heating condition, the first control layer and second control layer control the coolant droplet to leave the position underneath the light-emitting element.

Abstract: The present disclosure relates to development of microdevices on a substrate that can be released and transferred to a system substrate. The disclosure further relates to methods to integrate anchors to hold a microdevice to a substrate. The microdevices are in different configurations with respect to anchors, release layers, buffers layers and substrate.

Abstract: An integrated circuit device includes a first cell and a second cell apart from each other in a first lateral direction on a substrate, the first cell and the second cell each including a plurality of gate lines, an inter-cell isolation region between the first cell and the second cell, the inter-cell isolation region extending in a second lateral direction, a power line including portions overlapping a cell boundary of each of the first cell and the second cell in a vertical direction and a portion overlapping the inter-cell isolation region in the vertical direction, a plurality of dummy gate insulation lines, a bridge insulating pattern in contact with an end portion of each of the plurality of dummy gate insulation lines, and a via power rail passing through the bridge insulating pattern, the via power rail being connected to the power line.

Abstract: Embodiments described herein may be related to apparatuses, processes, systems, and/or techniques for electrically coupling components of a transistor structure together in order to perform a voltage contrast test to determine opens and shorts within the transistor structure. In embodiments, trench contacts (TCN) within a transistor structure may be electrically coupled together with an electrical connection that is electrically isolated from a power rail. In other embodiments, TCN may be electrically coupled using P-type epitaxial layers on a P-type substrate. Other embodiments may be described and/or claimed.

Abstract: Bonding strength of a connection portion bonded to a semiconductor element is measured. The semiconductor element includes a semiconductor substrate and a bond pad. In the semiconductor substrate, an element is formed, and a wiring region having a wiring for transmitting a signal of the element is disposed adjacent. The bond pad is disposed in the wiring region adjacent to a semiconductor substrate removal region, which is a region where the semiconductor substrate is removed, connected to the wiring, and bonded with a connection portion for connection to an outside. The semiconductor substrate removal region includes a region for measuring bonding strength of the bond pad and the connection portion.

Abstract: Electronic module (1) including an encapsulation (20), a carrier substrate (10) enclosed by the encapsulation (20) and having a component side (25) which has a first metallization layer (15) and on which at least one first electronic component (30) is arranged, wherein at least one second metallization layer (35) for at least one second electronic component (31), in particular for controlling the first electronic component (30), is provided on an outer side (A) of the encapsulation (2), wherein the encapsulation (20) has at least one plated-through hole (5) for electrical connection, in particular for direct electrical connection, of the first electronic component (30) and the second electronic component (31).

Abstract: A semiconductor device includes bit lines, gate electrodes, a gate insulation pattern, a channel structure, a metal oxide pattern and a metal pattern on a substrate. The bit lines extend in a first direction and are spaced apart from each other in a second direction. The gate electrodes are disposed on the bit lines, spaced apart from each other in the first direction, and extend in the second direction. The gate insulation pattern is formed on a sidewall in the first direction of the gate electrodes. The channel structure is formed on a sidewall in the first direction of the gate insulation pattern. The metal oxide pattern is formed on a sidewall in the first direction of the channel structure. The metal pattern is formed on a sidewall in the first direction of the metal oxide pattern.

Abstract: Embodiments of the present disclosure relate to the field of semiconductors, and provide a semiconductor structure and a manufacturing method thereof. The semiconductor structure includes: a base and a bit line that extends along a first direction; active structures, wherein the active structure includes at least two active layers arranged at intervals, the active layer includes a first source-drain region, a channel region, a second source-drain region, and a support region, and the bit line is connected to the first source-drain region; a word line extending along a second direction, wherein the word line is connected to an adjacent active structure, and the word line surrounds at least two channel regions included in the connected active structure; and a memory structure perpendicularly stacked on the base, where the memory structure is connected to the second source-drain region, and the memory structure surrounds the support region.

Abstract: An integrated circuit chip package and a method of fabricating the same are disclosed. The method includes forming a device layer on a substrate with a first die and a second die, forming an interconnect structure on the device layer, depositing an insulating layer on the interconnect structure, forming first and second conductive pads on the interconnect structure, forming first and second conductive vias on the first and second conductive pads, respectively, patterning a polymer layer to form first and second buffer layers with tapered side profiles on the first and second conductive vias, respectively, forming a trench in the substrate and between the first and second buffer layers, and dicing the substrate through the trench to separate the first die from the second die. Portions of the first and second conductive pads extend over the insulating layer.

Abstract: A semiconductor device includes: a second metal pattern electrically connected to a first semiconductor element and a second semiconductor element; a third metal pattern electrically connected to the second semiconductor element; a fifth metal pattern electrically connected to the third semiconductor element and a fourth semiconductor element; a sixth metal pattern electrically connected to the fourth semiconductor element; and a first conductive portion straddling the third metal pattern and the sixth metal pattern in plan view and electrically connecting the second metal pattern and the fifth metal pattern.