Abstract: A semiconductor memory device includes a bit line on a substrate and extending in a first direction parallel to a top surface of the substrate, a channel pattern connected to a top surface of the bit line and extending in a second direction perpendicular to the top surface of the substrate, a first drain pattern on the channel pattern, a first word line adjacent to a lower portion of the first drain pattern and the channel pattern, and a gate insulating layer between the lower portion of the first drain pattern and the first word line and between the channel pattern and the first word line. An energy band gap of a first material of the first drain pattern is greater than an energy band gap of a second material of the channel pattern.

Abstract: A display device includes a display panel, and a color conversion member disposed on the display panel. The color conversion member includes a plurality of partition walls disposed on the display panel and spaced apart from each other, and a color control part disposed between the plurality of partition walls. Each of the plurality of partition walls includes a first sub partition wall including a scattering body, and a second sub partition wall disposed on the first sub partition wall, and including a liquid repellent. The second sub partition wall has a higher light transmittance than the first sub partition wall.

Abstract: Memory cells, semiconductor devices, semiconductor stacked structures, and fabrication methods are provided. An example memory cell includes a capacitor and a transistor stacked over the capacitor in a compact configuration. The capacitor includes a floating gate, a high-k dielectric layer, and a metal gate. The metal gate extends horizontally from a first sidewall to a second sidewall and vertically from a bottom surface to a top surface. The transistor includes the metal gate and a gate dielectric layer disposed on the metal gate. The gate dielectric layer includes two side portions respectively disposed on the two sidewalls of the metal gate and, and a top portion disposed on the top surface of the metal gate. The transistor further includes two separate S/D regions respectively formed on the two side portions of the gate dielectric layer, and a channel region formed on the top portion of the gate dielectric layer.

Abstract: An image sensor includes an image sensor die, a light transmitting element, at least one anti-reflection coating and at least one anti-reflection structure. The image sensor die includes a photoelectric conversion layer and a micro lens layer. The micro lens layer is disposed above the photoelectric conversion layer for converging the light onto the photoelectric conversion layer. The light transmitting element is disposed above the micro lens layer, and a gap is formed between the light transmitting element and the micro lens layer, the light passes through the light transmitting element and then travels into the image sensor. The anti-reflection coating is at least disposed on an upper surface of the light transmitting element. The anti-reflection structure is disposed on at least one of a lower surface of the light transmitting element and the micro lens layer.

Abstract: A light emitting display device includes a first display area; and a second display area disposed adjacent to the first display area, wherein the second display area includes a pixel driving part, a main light-emitting element directly connected to the pixel driving part, and an additional light-emitting element connected to the main light-emitting element, the additional light-emitting element overlaps a peripheral driving part in a plan view, the peripheral driving part generates a signal provided to the pixel driving part, the main light-emitting element and the additional light-emitting element each include a first electrode, an emission layer, and a second electrode, the pixel driving part is electrically connected to the second electrode of the main light-emitting element and the second electrode of the additional light-emitting element, and the second electrode of the additional light-emitting element and the second electrode of the main light-emitting element are separated by a separator.

Abstract: A semiconductor device includes a lower structure; a vertical conductive line extending in a first direction which is perpendicular to a surface of the lower structure; a reservoir capacitor disposed over the lower structure to be spaced apart from the vertical conductive line; a bridge horizontal layer disposed between the vertical conductive line and the reservoir capacitor and extending horizontally in a second direction which is parallel to the surface of the lower structure; and a pair of horizontal layers extending in a third direction intersecting the bridge horizontal layer with the bridge horizontal layer interposed therebetween.

Abstract: A light-emitting device includes a base member, a frame member and a light-emitting element. The frame member is fixed to the base member and has one or more inner lateral surfaces and one or more outer lateral surfaces. The frame member includes a first part containing a wavelength conversion material and defining one part of the one or more inner lateral surfaces and one part of the one or more outer lateral surfaces, and a second part connected with the first part and defining another part of the one or more inner lateral surfaces and another part of the one or more outer lateral surfaces. The light emitting element has a light-emitting surface, and is configured to emit, from the light-emitting surface, light to be incident on the one part of the one or more inner lateral surfaces defined by the first part of the frame member.

Abstract: An integrated circuit structure includes a device layer including an upper device above a lower device. The upper device includes an upper source or drain region, and an upper source or drain contact coupled to the upper source or drain region. The lower device includes a lower source or drain region. A first conductive feature is below the device layer, where the first conductive feature is coupled to the lower source or drain region. A second conductive feature vertically extends through the device layer. In an example, the second conductive feature is to couple (i) the first conductive feature below the device layer and (ii) an interconnect structure above the device layer. Thus, the first and second conductive features facilitate a connection between the interconnect structure on the frontside of the integrated circuit and the lower source or drain region towards the backside of the integrated circuit.

Abstract: Structures having raised epitaxy on channel structure transistors are described. In an example, an integrated circuit structure includes a channel structure having multi-layer epitaxial source or drain structures thereon, the multi-layer epitaxial source or drain structures having a recess extending there through. A gate dielectric layer is on a bottom and along sides of the recess and laterally surrounded by the epitaxial source or drain structures. A gate electrode is on and laterally surrounded by the gate dielectric layer. The gate electrode has an uppermost surface below an uppermost surface of the gate dielectric layer.

Abstract: According to embodiments, a light emitting display device includes a light emitting diode (LED) positioned on a substrate and including an emission layer, a pixel definition layer including an opening corresponding to the emission layer, and a plurality of light-shielding linear patterns positioned on the pixel definition layer and the emission layer and extending in a first direction. The plurality of light-shielding linear patterns include a recess portion of a concave shape.

Abstract: An integrated circuit device includes a first-type active-region semiconductor structure extending and a second-type active-region semiconductor structure both extending in a first direction. The second-type active-region semiconductor structure is stacked with the first-type active-region semiconductor structure. The integrated circuit device also includes a front-side conductive layer above the two active-region semiconductor structures and a back-side conductive layer below the two active-region semiconductor structures. The integrated circuit device still includes a front-side power rail extending in the second direction in the front-side conductive layer and a back-side power rail extending in the second direction in the back-side conductive layer. The integrated circuit device further includes a first source conductive segment connected to the front-side power rail and a second source conductive segment connected to the back-side power rail.

Abstract: An integrated circuit (IC) structure includes a gate structure, source/drain epitaxial structures, a front-side interconnection structure, a backside dielectric layer, and a backside via. The source/drain epitaxial structures are respectively on opposite sides of the gate structure. The front-side interconnection structure is on front-sides of the source/drain epitaxial structures. The backside dielectric layer is on backsides of the source/drain epitaxial structures. The backside via extends through the backside dielectric layer to one of the source/drain epitaxial structures, and has a maximal lateral dimension larger than a lateral dimension of the source/drain epitaxial structure.

Abstract: A heterogeneous epitaxial structure formed on a SiC (silicon carbide) substrate. An intermediate layer comprising AlN is formed overlying the SiC substrate. The surface of the intermediate layer comprises AlN formed by lateral epitaxial growth. The lateral epitaxial growth merges to form the surface comprising a MELO layer (merged epitaxial lateral overgrowth). The intermediate layer includes a carbon layer underlying the MELO layer. At least one device layer comprising GaN (gallium nitride) is formed overlying the surface of the intermediate layer in which one or more semiconductor devices are formed. The carbon layer is heated to fracture portions of the intermediate layer to separate the SiC substrate from the intermediate layer. The SiC substrate is not consumed by the separation thereby allowing perpetual reuse in semiconductor wafer processing.

Abstract: Provided is a solid-state imaging device that readily accommodates a design change of a pixel chip or a circuit chip. The solid-state imaging device according to the present technology includes a pixel chip including a pixel having a photoelectric conversion element, at least one circuit chip including a circuit configured to process a signal generated in the pixel, and a connecting substrate electrically connecting the pixel chip and the circuit chip, in which the pixel chip, the connecting substrate, and the circuit chip are stacked in this order. It is possible to provide a solid-state imaging device that readily accommodates a design change of a pixel chip or a circuit chip on the basis of the solid-state imaging device according to the present technology.

Abstract: The present disclosure provides a display panel and a display apparatus. The display panel includes a first electrode layer, an electron transport layer, a light emitting layer, a hole transport layer, a hole injection layer, and a second electrode layer, which are sequentially stacked, a material of the hole injection layer includes a first metal oxide and a second metal oxide, which contain the same metal element, the number of outermost electrons of the metal element in the first metal oxide is different from the number of outermost electrons of the metal in the second metal oxide. In addition, the hole injection layer further includes a metal M and a third metal oxide MOy, the third metal oxide MOy is formed by an oxidation-reduction reaction between the metal M and the first metal oxide. The hole injection layer may be of a single layer or a multi-layer structure.

Abstract: A semiconductor device includes a substrate having first and second active patterns therein, which are spaced apart from each other. The first active pattern has a top surface that is elevated relative to a top surface of the second active pattern. A channel semiconductor layer is provided on the top surface of the first active pattern. A first gate pattern is provided, which includes a first insulating pattern, on the channel semiconductor layer. A second gate pattern is provided, which includes a second insulating pattern having a thickness greater than a thickness of the first insulating pattern, on the top surface of the second active pattern.

Abstract: Disclosed herein are techniques for micro-light emitting diodes (micro-LEDs). According to certain embodiments, a micro-LED device includes a micro-LED comprising a semiconductor mesa structure configured to emit light, a spacer layer on the micro-LED, and a micro-lens on the spacer layer and configured to extract and collimate the light emitted by the micro-LED, where a thickness of the spacer layer is selected such that a focal point of the micro-lens is at a front surface of the semiconductor mesa structure.

Abstract: An electronic device and a manufacturing method thereof are disclosed. The electronic device includes a substrate, an electronic element, a barrier layer, a light absorbing layer, and a filter layer. The electronic element is disposed on the substrate. The barrier layer is disposed on the substrate and surrounds a side surface of the electronic element. The light absorbing layer is disposed on the barrier layer. The filter layer is disposed on the electronic element.

Abstract: An integrated circuit (IC) device is described. The IC device includes a semiconductor-on-insulator (SOI) substrate having a first-type diffusion region. The IC device also includes a first, first-type transistor on the first-type diffusion region. The IC device further includes a second, first-type transistor on the first-type diffusion region. The IC device also includes a first, second-type implant region. The first, second-type implant region includes a gate overlap region partially overlapped with a gate region of the second, first-type transistor to provide a body contact of the second, first-type transistor and to couple a source region of the second, first-type transistor to a drain region of the first, first-type transistor in series.

Abstract: A method of forming a semiconductor structure includes providing a substrate with an array region, a peripheral region, and a transition region between the array region and the peripheral region. A patterned floating gate layer is formed on the array region and the peripheral region, and a stacked layer is conformally formed on the substrate, wherein a recess is formed over the transition region. A photoresist layer is formed on the substrate, and the photoresist layer is patterned to form an array region pattern on the stacked layer of the array region, wherein a portion of the photoresist layer remains at the bottom of the recess, and a recess pattern is formed. The array region pattern and the recess pattern are sequentially transferred to the stacked layer, the patterned floating gate layer and the substrate to form a plurality of arrays and a pair of blocking structures.