Abstract: A package includes a carrier substrate, a first die, and a second die. The first die includes a first bonding layer, a second bonding layer opposite to the first bonding layer, and an alignment mark embedded in the first bonding layer. The first bonding layer is fusion bonded to the carrier substrate. The second die includes a third bonding layer. The third bonding layer is hybrid bonded to the second bonding layer of the first die.

Abstract: Provided is a semiconductor package. The semiconductor package includes an image sensor chip including a first surface and a second surface opposite to each other in a first direction; a transparent substrate spaced apart from the second surface of the image sensor chip in a second direction, wherein the transparent substrate includes a first part and a second part with a width different from the first part; an adhesive layer disposed between the second surface of the image sensor chip and the first part of the transparent substrate; and a mold layer on the second part of the transparent substrate, wherein the mold layer comprises side surfaces that extend along the first part of the transparent substrate, and further extend along side surfaces of the adhesive layer and side surfaces of the image sensor chip, and not extending along the first surface of the image sensor chip.

Abstract: A transistor in an embodiment includes an oxide semiconductor layer on a substrate, the oxide semiconductor layer including a first region and a second region, a first gate electrode including a region overlapping the oxide semiconductor layer, the first gate electrode being arranged on a surface of the oxide semiconductor layer opposite to the substrate, a first insulating layer between the first gate electrode and the oxide semiconductor layer, and a first oxide conductive layer and a second oxide conductive layer between the oxide semiconductor layer and the substrate, the first oxide conductive layer and the second oxide conductive layer each including a region in contact with the oxide semiconductor layer.

Abstract: A device includes an organic insulating film having a contact hole in which an inclined face is formed, a pixel electrode formed along an inclined face of the contact hole and the organic insulating film, an intra-pixel wiring line coupling the pixel electrode to a TFT within the contact hole, a light-emitting layer formed on the organic insulating film to cover the pixel electrode, a light-emitting layer formed to overlap the light-emitting layer at least in the inclined face of the contact hole, and a common electrode formed on the light-emitting layer correspondingly to the pixel electrode.

Abstract: A method is provided. The method includes forming an interconnect structure electrically connected to a semiconductor device; forming a tantalum-based barrier layer over the interconnect structure; oxidizing the tantalum-based barrier layer to form a tantalum oxide over the tantalum-based barrier layer; and forming a metal layer over the tantalum oxide.

Abstract: A semiconductor device includes a low-density substrate, a high-density patch positioned inside a cavity in the low-density substrate, a first semiconductor die, and a second semiconductor die. The first semiconductor dies includes high-density bumps and low-density bumps. The second semiconductor die includes high-density bumps and low-density bumps. The high-density bumps of the first semiconductor die and the high-density bumps of the second semiconductor die are electrically connected to the high-density patch. The low-density bumps of the first semiconductor die and the low-density bumps of the second semiconductor die are electrically connected to the low-density substrate.

Abstract: Various embodiments of the present disclosure are directed towards a semiconductor device. The semiconductor device includes a semiconductor fin projecting from a substrate. Semiconductor nanostructures are disposed over the semiconductor fin. A gate electrode is disposed over the semiconductor fin and around the semiconductor nanostructures. A dielectric fin is disposed over the substrate. A dielectric structure is disposed over the dielectric fin. An upper surface of the dielectric structure is disposed over the upper surface of the gate electrode. A dielectric layer is disposed over the substrate. The dielectric fin laterally separates both the gate electrode and the semiconductor nanostructures from the dielectric layer. An upper surface of the dielectric layer is disposed over the upper surface of the gate electrode structure and the upper surface of the dielectric structure. A lower surface of the dielectric layer is disposed below the upper surface of the dielectric fin.

Abstract: A light emitting diode having an improved heat dissipation effect includes a light source unit emitting a light to a front surface and including a light emitting part, a first electrode pad, and a second electrode pad. The light emitting diode further includes a lead frame unit disposed on a rear surface of the light source unit and including first and second lead terminals respectively connected to the first and second electrode pads. The light emitting diode also includes at least one of the first and second lead terminals includes an upper conductive layer, an intermediate conductive layer, and a lower conductive layer which are disposed on different layers and electrically connected to one another.

Abstract: A device includes a first semiconductor chip including a first face, wherein a first contact pad is arranged over the first face. The device further includes a second semiconductor chip including a first face, wherein a first contact pad is arranged over the first face, wherein the first semiconductor chip and the second semiconductor chip are arranged such that the first face of the first semiconductor chip faces in a first direction and the first face of the second semiconductor chip faces in a second direction opposite to the first direction. The first semiconductor chip is located laterally outside of an outline of the second semiconductor chip.

Abstract: A light emitting device for a display including a light emitting structure including a first conductivity type semiconductor layer, an active layer, and a second conductivity type semiconductor layer, and having a side surface exposing the active layer, in which a portion of the second conductivity type semiconductor layer and the active layer along an edge of the light emitting structure is insulative in a thickness direction to define an insulation region, and the insulation region includes implanted ions.

Abstract: A light emitting device may include: a substrate including emission areas; a first electrode disposed on the substrate, and a second electrode spaced apart from the first electrode; at least one light emitting element disposed on the substrate, and including a first end and a second end; an insulating layer disposed on the light emitting element and allowing the first and second ends of the light emitting element to be exposed; a first contact electrode electrically connecting the first electrode with the first end of the light emitting element; a second contact electrode electrically connecting the second electrode with the second end of the light emitting element; and a passivation pattern disposed on each of the first and second contact electrodes. The first and second contact electrodes may be disposed on the insulating layer and spaced apart from each other and may be electrically separated from each other.

Abstract: A semiconductor structure includes a source/drain (S/D) feature; one or more channel semiconductor layers connected to the S/D feature; a gate structure engaging the one or more channel semiconductor layers; a first silicide feature at a frontside of the S/D feature; a second silicide feature at a backside of the S/D feature; and a dielectric liner layer at the backside of the S/D feature, below the second silicide feature, and spaced away from the second silicide feature by a first gap.

Abstract: A display device includes LEDs, a circuit board, an insulating layer, conductive posts, a control conductive plate, and a common conductive strip. The circuit board includes first pads and a second pad surrounding the first pads. The LEDs are on an insulating layer covering the first pads, each including a first and second electrode pad. The conductive posts are on and connected to a first portion of the first pads, and penetrate the insulation layer. The control conductive plate is electrically connected to one of the first electrode pads and the conductive posts. The common conductive strip is on the insulation layer and electrically connected to the second pad and a second electrode pad. Each first electrode pad is electrically connected to the first pads. A second portion of the first pads is completely covered by the insulation layer and overlapped with the common conductive strip and the insulation layer.

Abstract: A method includes a gate structure, gate spacers, a gate helmet, a metal cap, and a gate contact. The gate structure is over a substrate. The gate spacers are on either side of the gate structure. The gate helmet is over the gate structure and the gate spacers. The metal cap is in the gate helmet over the gate structure. The gate contact is over the metal cap. The gate contact forms an interface with the metal cap at a different level height than top segments of the gate spacers.

Abstract: The method for forming overlay marks includes: providing a substrate, a surface of the substrate having a mark layer and a first mask layer; forming first trenches and second trenches in the first mask layer; forming a spacer layer covering side walls of the first trenches and side walls of the second trenches; backfilling the first trenches and the second trenches; removing the spacer layer; and etching the mark layer and forming main overlay marks and dummy overlay marks.

Abstract: Donor substrate micro device stabilization structures and display structures are described. In an embodiment, a patterned electrically conductive layer is used to stabilize an array of micro devices on donor substrate with a plurality of tethers, which can be broken during a transfer sequence to transfer the array of micro devices from the donor substrate.

Abstract: A method of making a semiconductor device includes forming a first active region on a first side of a substrate. The method further includes forming a first source/drain (S/D) electrode surrounding a first portion of the first active region. The method further includes forming an S/D connect via extending through the substrate. The method further includes flipping the substrate. The method further includes forming a second active region on a second side of the substrate, wherein the second side of the substrate is opposite to the first side of the substrate. The method further includes forming a second S/D electrode surrounding a first portion of the second active region, wherein the S/D connect directly contacts both the first S/D electrode and the second S/D electrode.

Abstract: A microelectronic device comprises a conductive line and a transistor adjacent to the conductive line. The transistor comprises a channel material extending into the conductive line, the channel material contacting the conductive line in three dimensions, a dielectric material adjacent to the channel material, a conductive material adjacent to the dielectric material, and a passivation material adjacent to the channel material. The microelectronic device further comprises a conductive contact adjacent to the channel material, the conductive contact including a portion extending between opposing portions of the channel material. Related microelectronic devices, electronic devices, and related methods are also disclosed.

Abstract: A system and method are presented for the design and fabrication of arrays of vacuum photodiodes for application to solar power generation. In a preferred embodiment, each photodiode cell comprises a microfabricated enclosure with a hermetically sealed vacuum, an absorptive photocathode, and a transparent anode, wherein the photocathode and the anode are separated by a vacuum gap of less than about 20 micrometers. Light incident on the photocathode through the anode leads to a flux of electrons passing from the photocathode across the vacuum gap to the anode. In a further preferred embodiment, the photocathode is backed by a reflection layer with, e.g., controlled diffuse reflection, thus increasing the efficiency of energy extraction. An array of such cells may be manufactured using automated thin-film deposition and micromachining techniques.

Abstract: A method that forms a sacrificial fill material that can be selectively removed for forming a backside contact via for a transistor backside power rail. In some embodiments, the method may include performing an etching process on a substrate with an opening that is conformally coated with an oxide layer, wherein the etching process is an anisotropic dry etch process using a chlorine gas to remove the oxide layer from a field of the substrate and only from a bottom portion of the opening, and wherein the etching process forms a partial oxide spacer in the opening and increases a depth of the opening and epitaxially growing the sacrificial fill material in the opening by flowing a hydrogen chloride gas at a rate of approximately 60 sccm to approximately 90 sccm in a chamber pressure of approximately 1 Torr to approximately 100 Torr.