Patents Examined by Jonathan Han
  • Patent number: 11081661
    Abstract: The present invention provides a flexible organic light-emitting diode (OLED) panel, including: a flexible substrate which includes a channel; a buffer layer disposed on the second organic layer, the buffer layer including a buffer layer groove; a first block wall disposed on the buffer layer, the first block wall surrounding the buffer layer groove and defining a display region; a second block wall disposed on the buffer layer and over the channel, the second block wall surrounding the first block wall; and a packaging layer disposed in the display region, the packaging layer including an organic packaging layer, a portion of the organic packaging layer being disposed in the buffer layer groove and in contact with the flexible substrate.
    Type: Grant
    Filed: February 14, 2019
    Date of Patent: August 3, 2021
    Assignee: Wuhan China Star Optoelectronics Semiconductor Display Technology Co., Ltd.
    Inventor: Kerong Wu
  • Patent number: 11081467
    Abstract: A semiconductor device may include a bond pad/probe pad pair that includes a bond pad and a probe pad positioned to be adjacent to each other to form an L shape. The device may also include a through-silicon via (TSV) pad positioned to be at least partially or entirely inside the recess area of the L shape. The bond pad and the probe pad may each have an opening, and at least a portion of the opening of the bond pad may extend into a portion of the opening of the probe pad. The arrangement of the bond pad, the probe pad and the TSV may be implemented in a wafer-on-wafer (WOW) that includes multiple stacked wafers. A method of fabricating the TSV may include etching the stacked wafers to form a TSV opening that extends through the multiple wafers, and filling the TSV opening with conductive material.
    Type: Grant
    Filed: December 28, 2018
    Date of Patent: August 3, 2021
    Assignee: Micron Technology, Inc.
    Inventor: Tomohiro Kitano
  • Patent number: 11081587
    Abstract: There is provided a thin film transistor including: a substrate; a gate electrode and a first electrode in a single layer on the substrate; an active layer above the first electrode, an orthographic projection of the active layer on the substrate at least partially covers an orthographic projection of the first electrode on the substrate; a first insulation layer covering the gate electrode, the first electrode, the active layer, a portion of the substrate exposed between the gate electrode and the active layer, and another portion of the substrate exposed between the gate electrode and the first electrode; and a second electrode above the first insulation layer, an orthographic projection of the second electrode on the substrate at least partially covers the orthographic projection of the active layer on the substrate, and the second electrode is connected to the active layer through a via-hole in the first insulation layer.
    Type: Grant
    Filed: July 3, 2019
    Date of Patent: August 3, 2021
    Assignees: CHONGQING BOE OPTOELECTRONICS TECHNOLOGY CO., LTD., BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Hongru Zhou, Kai Wang, Kunkun Gao, Xiaonan Dong, Zhaojun Wang
  • Patent number: 11074517
    Abstract: A computer-implemented method includes training a classification model to produce a mapping from a set of feature vectors to a set of confidence levels. Each feature vector describes a respective term, and each confidence level indicates a likelihood that the respective term is a keyword. A plurality of program artifacts are tokenized into a plurality of terms. For each term in the plurality of terms, a respective feature vector is determined for describing the term, based on the plurality of program artifacts. For each term in the plurality of terms, based on the respective feature vector, using the mapping, a respective confidence level is determined for indicating a likelihood that the term is a keyword of the plurality of program artifacts.
    Type: Grant
    Filed: May 25, 2018
    Date of Patent: July 27, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Yan Luo, Seana Hogan, Monvorath Phongpaibul, John Carl DelMonaco
  • Patent number: 11075179
    Abstract: A method for forming a bond pad structure includes forming an interconnect structure on a semiconductor device, forming a passivation layer on the interconnect structure, forming at least one opening through the passivation layer, forming an oxidation layer at least in the opening, and forming a pad metal layer on the oxidation layer. A portion of the interconnect structure is exposed by the at least one opening.
    Type: Grant
    Filed: June 3, 2019
    Date of Patent: July 27, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Wen-Hao Cheng, Yen-Yu Chen, Chih-Wei Lin, Yi-Ming Dai
  • Patent number: 11069758
    Abstract: The present disclosure relates to the display technology, and provides an OLED display substrate, a method for manufacturing the OLED display substrate and a display device. The method includes: forming pixel definition layer transition patterns with metal; and oxidizing the pixel definition layer transition patterns to form an insulative pixel definition layer.
    Type: Grant
    Filed: June 10, 2019
    Date of Patent: July 20, 2021
    Assignees: HEFEI XINSHENG OPTOELECTRONICS TECHNOLOGY CO., LTD., BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Wei Song, Liangchen Yan, Ce Zhao, Dongfang Wang, Bin Zhou, Yuankui Ding, Jun Liu, Yingbin Hu, Wei Li
  • Patent number: 11069871
    Abstract: Provided is an organic white light emitting element (EL) including: a reflective electrode, a light extraction electrode, and an organic layer arranged therebetween, the organic layer including: a blue light emitting layer (BL); and a long-wavelength light emitting layer, the long-wavelength light emitting layer arranged between the BL and the reflective electrode, the BL provided at such a position as to satisfy Equation given below: z=?×?1/4? where z represents an optical distance between the reflective electrode and an interface of the BL on the reflective electrode side, ? represents a phase of light reflected by the reflective electrode in an emission wavelength region of the BL, and ?1 represents a wavelength in a visible light region, and the EL has a resonator structure defined between the reflective electrode and the light extraction electrode and has a maximum peak resonant wavelength in a blue light wavelength region.
    Type: Grant
    Filed: July 3, 2019
    Date of Patent: July 20, 2021
    Assignee: CANON KABUSHIKI KAISHA
    Inventor: Takayuki Ito
  • Patent number: 11062962
    Abstract: Semiconductor devices and fabrication methods are provided. An exemplary semiconductor device includes a semiconductor substrate having a first region. The first region includes a first middle region and a first edge region adjacent to and surrounding the first middle region; and a surface of the first middle region of the semiconductor substrate is higher than a surface of the first edge region of the semiconductor substrate. The semiconductor device also includes a plurality of first fins discretely formed on the first middle region of the semiconductor substrate; and an isolation structure formed on the first middle region of the semiconductor substrate and the first edge region of the semiconductor substrate and covering portions of sidewall surfaces of the first fins.
    Type: Grant
    Filed: July 3, 2019
    Date of Patent: July 13, 2021
    Assignees: Semiconductor Manufacturing International (Shanghai) Corporation, Semiconductor Manufacturing International (Beijing) Corporation
    Inventor: Fei Zhou
  • Patent number: 11062939
    Abstract: Embodiments of the present disclosure generally relate to the fabrication of integrated circuits. More particularly, the implementations described herein provide techniques for deposition of high quality gapfill. Some embodiments utilize chemical vapor deposition, plasma vapor deposition, physical vapor deposition and combinations thereof to deposit the gapfill. The gapfill is of high quality and similar in properties to similarly composed bulk materials.
    Type: Grant
    Filed: June 19, 2019
    Date of Patent: July 13, 2021
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Samuel E. Gottheim, Eswaranand Venkatasubramanian, Pramit Manna, Abhijit Basu Mallick
  • Patent number: 11055632
    Abstract: A method for generating a universal data signal interference for generating a manipulated data signal for deceiving a first machine learning system, which is configured to ascertain a semantic segmentation of a received one-dimensional or multidimensional data signal, The method includes a) ascertaining a training data set that includes pairs of data signals and associated desired semantic segmentations, b) generating the data signal interference, as a function of the data signals of the training data set, of the associated desired semantic segmentation, as well as of estimated semantic segmentations of the data signals acted upon by the data signal interference.
    Type: Grant
    Filed: April 9, 2018
    Date of Patent: July 6, 2021
    Assignee: Robert Bosch GmbH
    Inventors: Chaithanya Kumar Mummadi, Jan Hendrik Metzen, Volker Fischer
  • Patent number: 11049974
    Abstract: A semiconductor device having a reduced amount of oxygen vacancy in a channel formation region of an oxide semiconductor is provided. Further, a semiconductor device which includes an oxide semiconductor and has improved electric characteristics is provided. Furthermore, a methods for manufacturing the semiconductor device is provided. An oxide semiconductor film is formed; a conductive film is formed over the oxide semiconductor film at the same time as forming a low-resistance region between the oxide semiconductor film and the conductive film; the conductive film is processed to form a source electrode and a drain electrode; and oxygen is added to the low-resistance region between the source electrode and the drain electrode, so that a channel formation region having a higher resistance than the low-resistance region is formed and a first low-resistance region and a second low-resistance region between which the channel formation region is positioned are formed.
    Type: Grant
    Filed: March 30, 2020
    Date of Patent: June 29, 2021
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Hideomi Suzawa, Tetsuhiro Tanaka, Hirokazu Watanabe, Yuhei Sato, Yasumasa Yamane, Daisuke Matsubayashi
  • Patent number: 11049972
    Abstract: A method for forming a semiconductor device structure is provided. The method includes forming an epitaxial structure over a semiconductor substrate. The method also includes generating and applying plasma on an entire exposed surface of the epitaxial structure to form a modified region in the epitaxial structure. The plasma is directly applied on the source/drain structure without being filtered out, and the plasma includes ions with different charges. The method further includes forming a metal layer on the modified region and heating the metal layer and the modified region to form a metal-semiconductor compound region.
    Type: Grant
    Filed: May 8, 2020
    Date of Patent: June 29, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chia-Cheng Chen, Su-Hao Liu, Kuo-Ju Chen, Liang-Yin Chen
  • Patent number: 11048727
    Abstract: Systems and methods of automated feature selection and pattern discovery of multi-variate time-series include obtaining a multi-variate times-series from a network; preprocessing the multi-variate times-series to account for sampling intervals and missing data in the multi-variate times-series; determining a distance matrix for the multi-variate times-series which estimates correlation among features in the multi-variate times-series; performing clustering on the distance matrix; reducing dimensionality of the multi-variate times-series based on the clustering to provide a lower-dimensionality time-series; and providing the lower-dimensionality time-series to one or more applications configured to analyze the multi-variate times-series from the network, wherein the lower-dimensionality time-series provides similar information as the multi-variate time-series with fewer dimensions thereby improving computational complexity of the one or more applications.
    Type: Grant
    Filed: September 10, 2018
    Date of Patent: June 29, 2021
    Assignee: Ciena Corporation
    Inventors: Thomas Triplet, David Côté, Merlin Davies, Arslan Shahid, Kevin Kim, Yan Liu
  • Patent number: 11043545
    Abstract: The present disclosure provides a display substrate, a fabricating method thereof, and a display device. The display substrate includes a substrate; at least one pixel on a side of the substrate, the at least one pixel comprising a driving transistor, the driving transistor comprising a drain; an insulating layer on a side of the driving transistor away from the substrate, the insulating layer covering the driving transistor and having a first via hole opposite to the drain; an auxiliary conductive structure on a side of the insulating layer away from the substrate, and the auxiliary conductive structure connected to the drain through the first via hole; and a first planarization layer on a side of the auxiliary conductive structure away from the substrate, and having a second via hole disposed therein.
    Type: Grant
    Filed: August 9, 2019
    Date of Patent: June 22, 2021
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Zhen Song, Guoying Wang, Wei Li
  • Patent number: 11034578
    Abstract: A multi-layer sealing film for high seal yield is provided. In some embodiments, a substrate comprises a vent opening extending through the substrate, from an upper side of the substrate to a lower side of the substrate. The upper side of the substrate has a first pressure, and the lower side of the substrate has a second pressure different than the first pressure. The multi-layer sealing film covers and seals the vent opening to prevent the first pressure from equalizing with the second pressure through the vent opening. Further, the multi-layer sealing film comprises a pair of metal layers and a barrier layer sandwiched between metal layers. Also provided is a microelectromechanical systems (MEMS) package comprising the multilayer sealing film, and a method for manufacturing the multi-layer sealing film.
    Type: Grant
    Filed: May 13, 2020
    Date of Patent: June 15, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chih-Chien Yang, Ming-Lun Shih, Ren-Dou Lee, Jen-Hao Liu
  • Patent number: 11037932
    Abstract: A semiconductor arrangement includes an active region including a semiconductor device. The semiconductor arrangement includes a capacitor having a first electrode layer, a second electrode layer, and an insulating layer between the first electrode layer and the second electrode layer. At least three dielectric layers are between a bottom surface of the capacitor and the active region.
    Type: Grant
    Filed: April 22, 2019
    Date of Patent: June 15, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LIMITED
    Inventors: Chern-Yow Hsu, Chen-Jong Wang, Chia-Shiung Tsai, Shih-Chang Liu, Xiaomeng Chen
  • Patent number: 11037922
    Abstract: Circuits and methods for protecting a device are provided. A first device to be protected includes a gate dielectric of a first thickness. A second device includes a gate dielectric of a second thickness that is less than the first thickness. A gate is shared by the first device and the second device.
    Type: Grant
    Filed: April 15, 2020
    Date of Patent: June 15, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Kuo-Yu Chou, Shang-Fu Yeh, Yi-Ping Chao, Chih-Lin Lee
  • Patent number: 11024699
    Abstract: A display device may include an insulation layer, a wire directly contacting the insulation layer, a first electrode overlapping the insulation layer, an organic light emitting layer positioned on the first electrode, and a second electrode positioned on the organic light emitting layer. The wire may include an aluminum alloy that includes at least one of copper, vanadium, and silicon. The first electrode may include silver.
    Type: Grant
    Filed: July 11, 2019
    Date of Patent: June 1, 2021
    Inventors: Tae Young Kim, Jongwoo Park, Youn Jae Jung, Hyojung Kim
  • Patent number: 11024626
    Abstract: Apparatus and circuits including transistors with different threshold voltages and methods of fabricating the same are disclosed. In one example, a semiconductor structure is disclosed. The semiconductor structure includes: a substrate; an active layer that is formed over the substrate and comprises a plurality of active portions; a polarization modulation layer comprising a plurality of polarization modulation portions each of which is disposed on a corresponding one of the plurality of active portions; and a plurality of transistors each of which comprises a source region, a drain region, and a gate structure formed on a corresponding one of the plurality of polarization modulation portions. The transistors have at least three different threshold voltages.
    Type: Grant
    Filed: September 19, 2019
    Date of Patent: June 1, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventor: Chan-Hong Chern
  • Patent number: 11018068
    Abstract: Described herein are methods and apparatuses for packaging an ultrasound-on-a-chip. An ultrasound-on-a-chip may be coupled to a redistribution layer and to an interposer layer. Encapsulation may encapsulate the ultrasound-on-a-chip device and first metal pillars may extend through the encapsulation and electrically couple to the redistribution layer. Second metal pillars may extend through the interposer layer. The interposer layer may include aluminum nitride. The first metal pillars may be electrically coupled to the second metal pillars. A printed circuit board may be coupled to the interposer layer.
    Type: Grant
    Filed: July 3, 2019
    Date of Patent: May 25, 2021
    Assignee: Butterfly Network, Inc.
    Inventors: Jianwei Liu, Keith G. Fife