Abstract: A lighting device comprising: a first LED for generating light of a first chromaticity in a first chromaticity region defined by chromaticity coordinates (0.486, 0.410), (0.509, 0.340), (0.578, 0.405), and (0.537, 0.461); a second LED for generating light of a second chromaticity in a second chromaticity region defined by chromaticity coordinates (0.328, 0.495), (0.342, 0.390), (0.478, 0.444), and (0.464, 0.545); and a third LED for generating light of a third chromaticity in a third chromaticity region defined by chromaticity coordinates (0.195, 0.266), (0.205, 0.212), (0.286, 0.293), and (0.276, 0.328). Light generated by the device comprises a combination of light of the first, second, and third chromaticity and has a chromaticity that can be tunable by controlling power to the first, second and third LEDs.

Abstract: A microelectronic device including a nanosheet transistor that includes a first source/drain and a second source/drain. A frontside contact connected to the first source/drain and a backside contact connected to the second source/drain. A plurality of isolation layers located beneath the nanosheet transistor, and the second source/drain extends through the plurality of isolation layers to connect with the backside contact.

Abstract: An optoelectronic device including a light-emitting diode covered with a photoluminescent conversion layer based on a perovskite material.

Abstract: A lead frame formed of a plate-shaped copper material, at least one surface of which being smooth, comprising: a predetermined connection plating layer being provided at a portion to be connected for conduction of a semiconductor element on the smooth surface of the plate-shaped copper material; a portion where the smooth surface of the copper material exposed in an annular shape being provided around the connection plating layer; and an anodic oxide film of the copper material being provided at other portions. With this composition, the lead frame of the present disclosure, without having a roughening relaxation area, may be suitable for connection by solder connection or die attach material in the portion to be connected for conduction of semiconductor elements, may have excellent adhesion with sealing resin when a semiconductor package is manufactured by resin sealing, and may be manufactured efficiently and at a low cost.

Abstract: The present disclosure provides a semiconductor structure and a forming method thereof. The semiconductor structure includes a plurality of bit-line structures laterally spaced apart on a substrate, a landing pad between the bit-line structures, a metal oxynitride layer covered onto the top surface of the landing pad, and a capacitor structure vertically extending above the landing pad. The method of forming a semiconductor structure includes the following operations. A plurality of bit-line structures on a substrate is received. A landing pad is formed between the bit-line structures. A metal oxynitride layer is formed to cover the top surface of the landing pad. A sacrificial stack is formed on top of the metal oxynitride layer and the bit-line structures. A trench is formed in the sacrificial stack to expose the metal oxynitride layer. A capacitor structure is formed in the trench.

Abstract: An output circuit for a single-photon avalanche diode. In some embodiments, a system includes: a first sensing element; a bus line; a first pull-down circuit; a first pull-up element; and a second pull-up element, the first pull-up element, the second pull-up element, and the first pull-down circuit being connected to the bus line, the first pull-down circuit being connected to the first sensing element and configured to be activated based on a signal from the first sensing element, the first pull-up element having a lower drive strength than the first pull-down circuit.

Abstract: Embodiments of the present disclosure are directed to co-integrating multiple fin heights with bottom dielectric isolations for effective width tuning. In a non-limiting embodiment, a semiconductor structure includes a first shallow trench isolation (STI) region formed over a first portion of a substrate and a second STI region formed over a second portion of the substrate. A topmost surface of the second STI region is coplanar to a topmost surface of the first STI region. A first fin is formed in the first STI region and a second fin is formed in the second STI region. A topmost surface of the second fin is coplanar to a topmost surface of the first fin. A bottom dielectric isolation (BDI) region is positioned between the first fin and the substrate, thereby providing a first effective width and a second effective width for the first fin and second fin, respectively.

Abstract: A semiconductor structure includes heterojunction bipolar transistors arranged in parallel and disposed on a substrate. The semiconductor structure also includes a landing structure disposed at the edge of the HBTs on the substrate. The semiconductor structure also includes wiring disposed on the HBTs and connected to the landing structure. The semiconductor structure also includes an insulating layer disposed on the landing structure and having a via. The semiconductor structure also includes a bump disposed on the top surface of the insulating layer and connected to the wiring through the via. The sidewall of the landing structure has a recess in a top view.

Abstract: A microelectronic device comprising tiers of alternating dielectric materials and conductive materials, pillars extending through the tiers, and a doped dielectric material adjacent to the tiers. The doped dielectric material comprises a heterogeneous chemical composition comprising one or more dopants. Conductive contact structures are in the doped dielectric material. Additional microelectronic devices, microelectronic systems, and methods of forming microelectronic devices are disclosed.

Abstract: A package includes a mounting plate having a first part able to dissipate heat and a second part able to transmit and/or receive electrical signals. A cladding houses a first electronic chip and second electronic chip. The first electronic chip has a first semiconductor substrate (giving off, in operation, a first quantity of heat) mounted to the first part of the mounting plate and electrically connected by wires to the second part of the mounting plate. The second electronic chip has a second semiconductor substrate (giving off, in operation, a second quantity of heat) mounted to an interposer support including an interconnection network. An array of connection balls interconnects the interposer support to the first part of the mounting plate and the second part of the mounting plate. The first and second semiconductor substrates are different.

Abstract: A method of preparing a quantum dot, an optical member including the quantum dot prepared using the method, and an electronic device including the quantum dot are provided. The method includes forming a first particle including a core and a protective shell from a quantum dot composition including a precursor containing a tellurium (Te) element, a precursor containing a Group II element, and a precursor containing a Group VI element; purifying the first particle; and forming a second particle including a first shell by mixing the first particle with a first shell composition including the precursor containing a Group II element and the precursor containing a Group VI element and forming the first shell from the protective shell.

Abstract: The present disclosure relates to a photodetection device and an electronic apparatus that allow for reducing surface reflection from an on-chip microlens and suppressing deterioration of image quality. Provided is a photodetection device including: a plurality of pixels that have photoelectric conversion units; on-chip microlenses that are formed in such a way as to correspond to the individual pixels; and an antireflection film that is formed on a surface of the on-chip microlens, in which the antireflection film is constituted by a stacking of: a first inorganic film that is formed by a metal oxide film; and a second inorganic film that is formed on a surface of the first inorganic film and has a lower refractive index than the first inorganic film. The present disclosure can be applied to, for example, a CMOS solid-state imaging device.

Abstract: A semiconductor package includes: a carrier having a first side and an opposing second side; a semiconductor die arranged on the first side of the carrier; a heat conductor part arranged on the second side of the carrier; an encapsulation body encapsulating the semiconductor die, wherein the heat conductor part is exposed from the encapsulation body, and wherein the heat conductor part has a different material composition than the encapsulation body; and a scratch protection layer covering the heat conductor part, wherein the scratch protection layer has a hardness which is at least five times higher than a hardness of the heat conductor part.

Abstract: This application discloses a unit structure of a silicon photomultiplier tube, including a first conductive type heavily doped first electrode region located on a first side of the shallow trench isolation, a second conductive type heavily doped second electrode region located on a second side, and a quenching resistor located on a top surface of the shallow trench isolation. A photosensitive layer is formed in the silicon substrate at bottoms of the first electrode region, the shallow trench isolation and the second electrode region. The first electrode region, the photosensitive layer and the second electrode region form a Geiger mode avalanche photodiode. A first end of the quenching resistor is connected to the first electrode region through a first metal interconnect structure. A second end of the quenching resistor is connected to a first electrode. The second electrode region is connected to a second electrode.

Abstract: A phosphor powder including phosphor particles of a phosphor represented by a general formula Mx(Si, Al)2(N, O)3±y and in which a part of M is substituted with a Ce element, the phosphor powder includes phosphor particles in which a Si/Al atomic ratio is equal to or more than 1.5 and equal to or less than 6, an O/N atomic ratio is equal to or more than 0 and equal to or less than 0.1, 5 to 50 mol % of M is Li, and 0.5 to 10 mol % of M is Ce. In a case where a volume-based cumulative 10% particle size, a volume-based cumulative 50% particle size, and a volume-based cumulative 90% particle size of this phosphor powder measured by a laser diffraction scattering method are defined as D10, D50, and D90, respectively, (D90?D10)/D50 is equal to or more than 0.7 and equal to or less than 1.1.

Abstract: A semiconductor device having simplicity in design and improved performance and methods for fabricating the same are provided. The semiconductor device includes a substrate including a frontside and a backside opposite the frontside, an electronic device on the frontside of the substrate, an interlayer insulating layer covering the electronic device, a frontside wiring structure on the interlayer insulating layer, a backside wiring structure on the backside of the substrate, and at least one unit chain connecting the electronic device with the backside wiring structure, the unit chain including a through plug passing through the substrate, a connection contact on the interlayer insulating layer, a first chain plug passing through the interlayer insulating layer to connect the through plug with the connection contact, and a second chain plug passing through the interlayer insulating layer to be connected to the through plug.

Abstract: A semiconductor memory device includes a bit line on a substrate and extending in a first direction parallel to a top surface of the substrate, a channel pattern connected to a top surface of the bit line and extending in a second direction perpendicular to the top surface of the substrate, a first drain pattern on the channel pattern, a first word line adjacent to a lower portion of the first drain pattern and the channel pattern, and a gate insulating layer between the lower portion of the first drain pattern and the first word line and between the channel pattern and the first word line. An energy band gap of a first material of the first drain pattern is greater than an energy band gap of a second material of the channel pattern.

Abstract: A display device includes a display panel, and a color conversion member disposed on the display panel. The color conversion member includes a plurality of partition walls disposed on the display panel and spaced apart from each other, and a color control part disposed between the plurality of partition walls. Each of the plurality of partition walls includes a first sub partition wall including a scattering body, and a second sub partition wall disposed on the first sub partition wall, and including a liquid repellent. The second sub partition wall has a higher light transmittance than the first sub partition wall.

Abstract: Memory cells, semiconductor devices, semiconductor stacked structures, and fabrication methods are provided. An example memory cell includes a capacitor and a transistor stacked over the capacitor in a compact configuration. The capacitor includes a floating gate, a high-k dielectric layer, and a metal gate. The metal gate extends horizontally from a first sidewall to a second sidewall and vertically from a bottom surface to a top surface. The transistor includes the metal gate and a gate dielectric layer disposed on the metal gate. The gate dielectric layer includes two side portions respectively disposed on the two sidewalls of the metal gate and, and a top portion disposed on the top surface of the metal gate. The transistor further includes two separate S/D regions respectively formed on the two side portions of the gate dielectric layer, and a channel region formed on the top portion of the gate dielectric layer.

Abstract: An image sensor includes an image sensor die, a light transmitting element, at least one anti-reflection coating and at least one anti-reflection structure. The image sensor die includes a photoelectric conversion layer and a micro lens layer. The micro lens layer is disposed above the photoelectric conversion layer for converging the light onto the photoelectric conversion layer. The light transmitting element is disposed above the micro lens layer, and a gap is formed between the light transmitting element and the micro lens layer, the light passes through the light transmitting element and then travels into the image sensor. The anti-reflection coating is at least disposed on an upper surface of the light transmitting element. The anti-reflection structure is disposed on at least one of a lower surface of the light transmitting element and the micro lens layer.