Patents Examined by Jonathan Han
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Patent number: 11737292Abstract: Systems and methods for organic semiconductor devices with sputtered contact layers are provided. In one embodiment, an organic semiconductor device comprises: a first contact layer comprising a first sputter-deposited transparent conducting oxide; an electron transport layer interfacing with the first contact layer; a second contact layer comprising a second sputter-deposited transparent conducting oxide; a hole transport layer interfacing with the second contact layer; and an organic semiconductor active layer having a first side facing the electron transport layer and an opposing second side facing the hole transport layer; wherein either the electron transport layer or the hole transport layer comprises a buffering transport layer.Type: GrantFiled: November 30, 2020Date of Patent: August 22, 2023Assignees: SolarWindow Technologies, Inc., Alliance for Sustainable Energy, LLCInventors: Scott R. Hammond, Marinus Franciscus Antonius Maria van Hest
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Patent number: 11729966Abstract: A DRAM device includes an isolation region defining source and drain regions in a substrate, a first bit line structure connected to the source region, a second bit line structure disposed on the isolation region, an inner spacer vertically extending on a first sidewall of the first bit line structure, an air gap is between the inner spacer and an outer spacer, a storage contact between the first and second bit line structures and connected to the drain region, a landing pad structure vertically on the storage contact, and a storage structure vertically on the landing pad structure. The sealing layer seals a top of the first air gap. The sealing layer includes a first sealing layer on a first sidewall of a pad isolation trench, and a second sealing layer on a second sidewall of the pad isolation trench and separated from the first sealing layer.Type: GrantFiled: April 18, 2022Date of Patent: August 15, 2023Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Yoongoo Kang, Wonseok Yoo, Hokyun An, Kyungwook Park, Dain Lee
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Patent number: 11721793Abstract: A display device includes: a display module; a driving chip assembly electrically connected to the display module and including a driving chip and a heat dissipator at least partially surrounding the driving chip; and a main circuit board electrically connected to the driving chip assembly and contacting the heat dissipator.Type: GrantFiled: November 11, 2020Date of Patent: August 8, 2023Assignee: Samsung Display Co., Ltd.Inventor: Yeongsang Suh
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Patent number: 11721682Abstract: A light emitting device including a plurality of element structures each including a submount, a light emitting element, and a light transmissive member, in this order. The light emitting device further includes a first cover member holding the element structures by covering lateral faces of each of the element structures.Type: GrantFiled: January 12, 2022Date of Patent: August 8, 2023Assignee: NICHIA CORPORATIONInventors: Takashi Ishii, Dai Wakamatsu, Hiroaki Kageyama
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Patent number: 11710770Abstract: A semiconductor device includes a substrate having a first region and a second region, first and second nanowires disposed sequentially on the substrate in the first region, and extending respectively in a first direction, third and fourth nanowires disposed sequentially on the substrate in the second region, and extending respectively in the first direction, a first inner spacer between the first nanowire and the second nanowire, and including hydrogen of a first hydrogen mole fraction, and a second inner spacer between the third nanowire and the fourth nanowire, and including hydrogen of a second hydrogen mole fraction that is greater than the first hydrogen mole fraction.Type: GrantFiled: January 14, 2022Date of Patent: July 25, 2023Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Woo Cheol Shin, Sun Wook Kim, Seung Min Song, Nam Hyun Lee
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Patent number: 11705452Abstract: Various embodiments of the present disclosure are directed towards a semiconductor device. The semiconductor device includes a semiconductor fin projecting from a substrate. Semiconductor nanostructures are disposed over the semiconductor fin. A gate electrode is disposed over the semiconductor fin and around the semiconductor nanostructures. A dielectric fin is disposed over the substrate. A dielectric structure is disposed over the dielectric fin. An upper surface of the dielectric structure is disposed over the upper surface of the gate electrode. A dielectric layer is disposed over the substrate. The dielectric fin laterally separates both the gate electrode and the semiconductor nanostructures from the dielectric layer. An upper surface of the dielectric layer is disposed over the upper surface of the gate electrode structure and the upper surface of the dielectric structure. A lower surface of the dielectric layer is disposed below the upper surface of the dielectric fin.Type: GrantFiled: April 26, 2022Date of Patent: July 18, 2023Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Zhi-Chang Lin, Huan-Chieh Su, Kuo-Cheng Chiang
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Patent number: 11705522Abstract: A semiconductor device having a reduced amount of oxygen vacancy in a channel formation region of an oxide semiconductor is provided. Further, a semiconductor device which includes an oxide semiconductor and has improved electric characteristics is provided. Furthermore, a methods for manufacturing the semiconductor device is provided. An oxide semiconductor film is formed; a conductive film is formed over the oxide semiconductor film at the same time as forming a low-resistance region between the oxide semiconductor film and the conductive film; the conductive film is processed to form a source electrode and a drain electrode; and oxygen is added to the low-resistance region between the source electrode and the drain electrode, so that a channel formation region having a higher resistance than the low-resistance region is formed and a first low-resistance region and a second low-resistance region between which the channel formation region is positioned are formed.Type: GrantFiled: June 25, 2021Date of Patent: July 18, 2023Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Shunpei Yamazaki, Hideomi Suzawa, Tetsuhiro Tanaka, Hirokazu Watanabe, Yuhei Sato, Yasumasa Yamane, Daisuke Matsubayashi
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Patent number: 11706923Abstract: A semiconductor memory device including: a common source line; a substrate on the common source line; a plurality of gate electrodes arranged on the substrate and spaced apart from each other in a first direction perpendicular to a top surface of the common source line; a plurality of insulation films arranged among the plurality of gate electrodes; a plurality of channel structures penetrating through the plurality of gate electrodes and the plurality of insulation films in the first direction; and a plurality of residual sacrificial films arranged on the substrate and spaced apart from each other in the first direction, wherein the plurality of gate electrodes are disposed on opposite sides of the plurality of residual sacrificial films.Type: GrantFiled: September 30, 2021Date of Patent: July 18, 2023Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventor: Geun-won Lim
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Patent number: 11699653Abstract: A semiconductor apparatus comprising a first substrate, a second substrate coupled with the first substrate via an insulating member, a third substrate coupled to the first substrate and disposed on the opposite side to the second substrate and a conductive layer including an electrode disposed between the first and second substrate is provided. A through via is disposed so as to pass through the second substrate and a part of the insulating member to reach the electrode. An opening is arranged overlapping the electrode in the first substrate and a part of the insulating member. First and second resin layers are disposed between the electrode and the third substrate, and the first resin layer is disposed within the opening, is disposed between the electrode and the second resin layer and has a different Young's modulus from the second resin layer.Type: GrantFiled: July 30, 2020Date of Patent: July 11, 2023Assignee: CANON KABUSHIKI KAISHAInventor: Yuichi Kazue
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Patent number: 11699715Abstract: An optoelectronic assembly includes an integrated circuit (IC) chip including, on its front side, a photoconversion region and first electrical contact pads disposed alongside the photoconversion region. A circuit substrate contains a cavity into which the IC chip is inserted through the lower side and has a window opening through the upper side in communication with the cavity such that the photoconversion region of the IC chip is exposed through the window. The circuit substrate includes electrical circuit traces, which include second electrical contact pads disposed within the cavity alongside the window so as to contact the first electrical contact pads on the front side of the IC chip within the cavity. A base includes a stiff, heat-conducting material, to which the lower side of the circuit substrate is fixed. A malleable heat-conducting layer is compressed between the rear side of the IC chip and the base.Type: GrantFiled: September 6, 2020Date of Patent: July 11, 2023Assignee: APPLE INC.Inventor: Yazan Z. Alnahhas
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Patent number: 11699674Abstract: A method of forming a semiconductor device includes applying an adhesive material in a first region of an upper surface of a substrate, where applying the adhesive material includes: applying a first adhesive material at first locations of the first region; and applying a second adhesive material at second locations of the first region, the second adhesive material having a different material composition from the first adhesive material. The method further includes attaching a ring to the upper surface of the substrate using the adhesive material applied on the upper surface of the substrate, where the adhesive material is between the ring and the substrate after the ring is attached.Type: GrantFiled: August 23, 2021Date of Patent: July 11, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Kuan-Yu Huang, Li-Chung Kuo, Sung-Hui Huang, Shang-Yun Hou, Tsung-Yu Chen, Chien-Yuan Huang
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Patent number: 11690225Abstract: A semiconductor device includes: an alternating stack that is disposed over a lower structure and includes gate electrodes and dielectric layers which are staked alternately; a memory stack structure that includes a channel layer extending to penetrate through the alternating stack, and a memory layer surrounding the channel layer; a source contact layer in contact with a lower outer wall of the vertical channel layer and disposed between the lower structure and the alternating stack; a source contact plug spaced apart from the memory stack structure and extending to penetrate through the alternating stack; and a sealing spacer suitable for sealing the gate electrodes and disposed between the source contact plug and the gate electrodes. The sealing spacer has an etch resistance that is different from an etch resistance of the dielectric layers.Type: GrantFiled: January 26, 2022Date of Patent: June 27, 2023Assignee: SK hynix Inc.Inventor: Jin-Ha Kim
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Patent number: 11688809Abstract: A semiconductor device structure includes a fin structure, a semiconductive capping layer, an oxide layer, and a gate structure. The fin structure protrudes above a substrate. The semiconductive capping layer wraps around three sides of a channel region of the fin structure. The oxide layer wraps around three sides of the semiconductive capping layer. A thickness of a top portion of the semiconductive capping layer is less than a thickness of a top portion of the oxide layer. The gate structure wraps around three sides of the oxide layer.Type: GrantFiled: April 17, 2021Date of Patent: June 27, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Kuo-Cheng Ching, Kuan-Ting Pan, Kuan-Lun Cheng, Chih-Hao Wang
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Patent number: 11682502Abstract: A method of fabricating a polymer wire according to the present embodiment includes preparing an electrode platform having a micro gap, forming a plurality of single polymer wires on the electrode platform, and a heat treatment operation of aggregating the plurality of single polymer wires to form an aggregated polymer wire.Type: GrantFiled: May 28, 2020Date of Patent: June 20, 2023Assignee: Industry-Academic Cooperation Foundation, Yonsei UniversityInventors: Jongbaeg Kim, Yongkeun Oh, Dae-Sung Kwon
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Patent number: 11682639Abstract: A device includes an interconnect structure, a barrier multi-layer structure, an oxide layer, a pad metal layer, and a passivation layer. The barrier multi-layer structure is over the interconnect structure, the barrier multi-layer structure includes a first metal nitride layer and a second metal nitride layer over the first metal nitride layer. The oxide layer is over the barrier multi-layer structure, in which the oxide layer is an oxide of the second metal nitride layer of the barrier multi-layer structure. The pad metal layer is over the oxide layer. The passivation layer is in contact with the barrier multi-layer structure, the oxide layer, and the pad metal layer.Type: GrantFiled: July 22, 2021Date of Patent: June 20, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Wen-Hao Cheng, Yen-Yu Chen, Chih-Wei Lin, Yi-Ming Dai
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Patent number: 11676874Abstract: Described herein are methods and apparatuses for packaging an ultrasound-on-a-chip. An ultrasound-on-a-chip may be coupled to a redistribution layer and to an interposer layer. Encapsulation may encapsulate the ultrasound-on-a-chip device and first metal pillars may extend through the encapsulation and electrically couple to the redistribution layer. Second metal pillars may extend through the interposer layer. The interposer layer may include aluminum nitride. The first metal pillars may be electrically coupled to the second metal pillars. A printed circuit board may be coupled to the interposer layer.Type: GrantFiled: March 4, 2021Date of Patent: June 13, 2023Assignee: BFLY OPERATIONS, INC.Inventors: Jianwei Liu, Keith G. Fife
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Patent number: 11676963Abstract: An integrated circuit device includes a fin-type active region protruding from a substrate and extending in a first direction, a plurality of semiconductor patterns disposed apart from an upper surface of the fin-type active region, the plurality of semiconductor patterns each including a channel region; a gate electrode surrounding the plurality of semiconductor patterns, extending in a second direction perpendicular to the first direction, and including a main gate electrode, which is disposed on an uppermost semiconductor pattern of the plurality of semiconductor patterns and extends in the second direction, and a sub-gate electrode disposed between the plurality of semiconductor patterns; a spacer structure disposed on both sidewalls of the main gate electrode; and a source/drain region connected to the plurality of semiconductor patterns, disposed at both sides of the gate electrode, and contacting a bottom surface of the spacer structure.Type: GrantFiled: January 26, 2022Date of Patent: June 13, 2023Assignee: Samsung Electronics Co., Ltd.Inventors: Seungryul Lee, Yongseung Kim, Jungtaek Kim, Pankwi Park, Dongchan Suh, Moonseung Yang, Seojin Jeong, Minhee Choi, Ryong Ha
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Patent number: 11676858Abstract: Embodiments of the present disclosure generally relate to the fabrication of integrated circuits. More particularly, the implementations described herein provide techniques for deposition of high quality gapfill. Some embodiments utilize chemical vapor deposition, plasma vapor deposition, physical vapor deposition and combinations thereof to deposit the gapfill. The gapfill is of high quality and similar in properties to similarly composed bulk materials.Type: GrantFiled: June 29, 2021Date of Patent: June 13, 2023Assignee: APPLIED MATERIALS, INC.Inventors: Samuel E. Gottheim, Eswaranand Venkatasubramanian, Pramit Manna, Abhijit Basu Mallick
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Patent number: 11670743Abstract: A light emitting device includes: a substrate; a plurality of light emitting elements mounted on the substrate; a covering member disposed on the substrate between adjacent ones of the light emitting elements such that an upper surface of the covering member is substantially coplanar with upper surfaces of the light emitting elements, wherein the covering member is a molded body containing an inorganic material powder and a binder; and a light transmissive member disposed on or above the plurality of light emitting elements.Type: GrantFiled: August 7, 2020Date of Patent: June 6, 2023Assignee: NICHIA CORPORATIONInventor: Takayuki Igarashi
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Patent number: 11670680Abstract: A semiconductor device including: an active pattern on a substrate, the active pattern including a recess, the recess having a āVā shape; a growth prevention pattern on the recess; gate structures on portions of the active pattern at opposite sides of the recess; channels spaced apart from each other in a vertical direction perpendicular to an upper surface of the substrate, each of the channels extending through one of the gate structures; and a source/drain layer on the growth prevention pattern, the source/drain layer contacting the channels.Type: GrantFiled: December 22, 2021Date of Patent: June 6, 2023Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Sujin Jung, Kihwan Kim, Sunguk Jang, Youngdae Cho