Abstract: A document information managing apparatus includes: a storage storing document information and a first reference image in correspondence with each other, the first reference image being formed by changing a size of an output image of the document information based upon first magnification; a producing unit producing a second reference image having a size changed based upon second magnification smaller than the first magnification in relation to the document information when the size of the output image is larger than a predetermined size; a display displaying the first reference image when the size of the output image is smaller than the predetermined size, and displaying the second reference image when the size of the output image is larger than the predetermined size; and a display determining unit, when the second reference image is selected, controlling the display to display the first reference image relating to the selected second reference image.

Abstract: A system and method for processing graphics data which requires less read and write bandwidth. The graphics processing system includes an embedded memory array having at least three separate banks of single-ported memory in which graphics data are stored. A memory controller coupled to the banks of memory writes post-processed data to a first bank of memory while reading data from a second bank of memory. A synchronous graphics processing pipeline processes the data read from the second bank of memory and provides the post-processed graphics data to the memory controller to be written back to a bank of memory. The processing pipeline concurrently processes an amount of graphics data at least equal to that included in a page of memory. A third bank of memory is precharged concurrently with writing data to the first bank and reading data from the second bank in preparation for access when reading data from the second bank of memory is completed.

Abstract: A memory architecture includes a memory controller coupled to multiple modules. Each module includes a computing engine coupled to a shared memory. Each computing engine is capable of receiving instructions from the memory controller and processing the received instructions. The shared memory is configured to store main memory data and graphical data. Certain computing engines are capable of processing graphical data. The memory controller may include a graphics controller that provides instructions to the computing engine. An interconnect on each module allows multiple modules to be coupled to the memory controller.

Abstract: The present disclosure includes, among other things, systems, methods and program products for translating RenderMan shading language code.

Abstract: Embodiments of the present invention comprise methods, systems, and apparatus for multi-domain markers.

Abstract: Certain embodiments of the present invention provide a method for clinical presentation of a radiological study including: associating a customizable set of rules with image data corresponding to at least a portion of the radiological study; and rendering automatically the image data to form volumetric data; and navigating automatically the volumetric data with the customizable set of rules to present a navigated the at least a portion of the radiological study to a user. In an embodiment, the system further includes halting the navigating automatically the volumetric data from an interaction by the user. In an embodiment, the rendering automatically the image data is initiated from an interaction by the user. In an embodiment, the navigating automatically the volumetric data is initiated from an interaction by the user. In an embodiment, both the rendering automatically the image data and the navigating automatically the volumetric data are initiated an interaction by the user.

Abstract: A data processing apparatus includes a plurality of processing elements arranged in a single instruction multiple data array for processing data relating to graphical primitives. Vertex data relating to graphical primitives is used as feedback data for the processing elements for additional processing.

Abstract: A bit block transfer (Bitblt) circuit includes a read register, a write register, a bit shifting circuit and an overflowing register. The read register stores decomposition data including original data. The bit shifting circuit shifts the decomposition data in the read register to the write register and shifts bits of the decomposition data in the write register such that an initial bit of the original data of the decomposition data is situated apart from an initial address of the write register by a bit-shifting amount. The overflowing register coupled to the write register stores overflowing data of the original data overflowing from a memory length of the write register when the bits of the decomposition data in the write register are being shifted. The write register outputs and writes the decomposition data therein to a memory cell of a first memory.

Abstract: A data processing apparatus and method are provided for tracing activities of a shader program executed on shader circuitry of a data processing apparatus. The data processing apparatus comprises shader circuitry which is responsive to input data for a pixel to execute a shader program to generate a color value for the pixel. The shader program has multiple execution paths via which the color value may be generated, and which execution path is taken is dependent on the input data. An image buffer having a plurality of storage locations is provided, with each storage location being used to store the color value generated by the shader circuitry for an associated pixel. In a trace mode of operation, execution of the shader program by the shader circuitry causes a trace vector to be generated containing a plurality of items of execution path information indicative of the execution path taken, the trace vector comprising a plurality of fields, each field being used to store one item of execution path information.

Abstract: A Video Card with standard video output and a Network Ethernet port output of compressed digital video output that represents the image seen by a monitored computer user. A custom video card software driver is used to set up the dual display video controller configurations that assist with the functioning of the digital video compression that is a hardware combination of Run-Length, Huffman encoding and MPEG located on the same monitored user video card. One of the video controller's I2C ports is used to control the compression video circuits and as the pathway for the custom Ethernet communications, thus avoiding an additional costly connection to the user's main computer bus. The first video stream from the dual head video controller chip is used for regular viewing by the local PC (personal computer) user.

Abstract: The illustrative embodiments described herein provide a computer implemented method, apparatus, and computer program product for generating tile sizes associated with an image presented by a web based image system. An optimal threshold memory size for tiles associated with the image is identified. The image is then divided into tiles of equal physical dimensions and placed into a set of subdivided tiles. The memory size of each tile within the set of subdivided tiles is compared to the threshold memory size. Tiles having a memory size less than or equal to the threshold memory size are deleted from the set of subdivided tiles and stored. Tiles having a memory size greater than the threshold memory size are subdivided into tiles of smaller physical dimensions. The smaller tiles are placed back in the set of subdivided tiles. The process repeats until no tiles exist within the set of subdivided tiles.

Abstract: A system and method for representing multiple prefetchable memory resources, such as frame buffers coupled to graphics devices, as a unified prefetchable memory space for access by a software application. A graphics surface may be processed by multiple graphics devices, with portions of the surface residing in separate frame buffers, each frame buffer coupled to one of the multiple graphics devices. One or more redirection regions may be specified within the unified prefetchable memory space. Accesses within a redirection region are transmitted to a prefetchable memory of a single graphics device. Accesses within the unified prefetchable memory space, but outside of any redirection region may be broadcast to all of the prefetchable memories of the multiple graphics devices.

Abstract: In an information processing apparatus (1) according to the invention, a GMCH (13) is connected to a CPU (11) through a CPU bus (12), and an ICH (15) is connected to the GMCH (13) through a dedicated bus (14). The GMCH (13) includes a graphics controller (131) which borrows a part of a memory (171) mounted to a memory card (17) in order to execute display processing. A graphics card (19) can be connected to the GMCH (13). In this case, a graphics controller (131) becomes a stop state. While the graphics card (19) is connected to the GMCH (13), the CPU (11) instructs the graphics controller (13) to execute processing other than display control processing, for example, processing such as MC and IDCT. As a result, it is possible to reduce a load applied to the CPU (11).

Abstract: Circuits, methods, and apparatus for graphically displaying performance metrics of processors such as graphics processing units in multiple processor systems. Embodiments of the present invention may provide metric information regarding operations in alternate-frame rendering, split-frame rendering, or other modes of operation. One embodiment of the present invention provides data in split-frame rendering mode including load balancing, graphics processing unit utilization, frame rate, and other types of system information in a graphical manner. Another exemplary embodiment of the present invention provides graphical information regarding graphics processing unit utilization, frame rate, and other system information while operating in the alternate-frame rendering mode.

Abstract: A graphics system including a custom graphics and audio processor produces exciting 2D and 3D graphics and surround sound. The system includes a graphics and audio processor including a 3D graphics pipeline and an audio digital signal processor. A memory controller performs a wide range of memory control related functions including arbitrating between various competing resources seeking access to main memory, handling memory latency and bandwidth requirements of the resources requesting memory access, buffering writes to reduce bus turn around, refreshing main memory, and protecting main memory using programmable registers. The memory controller minimizes memory read/write switching using a “global” write queue which queues write requests from various diverse competing resources. In this fashion, multiple competing resources for memory writes are combined into one resource from which write requests are obtained.

Abstract: Graphics resources are virtualized through an interlace between graphics hardware and graphics clients. The interface allocates the graphics resources across multiple graphics clients, processes commands for access to the graphics resources from the graphics clients, and resolves conflicts for the graphics resources among the clients.

Abstract: Methods and apparatuses for dynamic virtual frame buffer management. At least one embodiment of the present invention dynamically enables or disables the use of a virtual frame buffer, which is not under control of graphics hardware of a data processing system, without restarting the graphical user interface system (e.g., the window system) of the data processing system. For example, in response to the addition or removing of a frame buffer that is under control of a graphics controller (e.g., due to the activation or deactivation of the graphics controller, or the hot plug-in or hot disconnection of the graphics controller), the virtual frame buffer is disabled or enabled respectively.

Abstract: Graphics resources are virtualized through an interface between graphics hardware and graphics clients. The interface allocates the graphics resources across multiple graphics clients, processes commands for access to the graphics resources from the graphics clients, and resolves conflicts for the graphics resources among the clients.

Abstract: An image processing system may perform various tasks in an effort to evenly distribute workload amongst workload managers. According to one embodiment of the invention, the image processing system may divide a frame of pixels into different regions and assign responsibility for the regions to different workload managers in order to evenly distribute workload. The workload managers may be responsible for performing operations relating to determining or maintaining the color of the pixel within the region or regions which they are responsible. According to another embodiment of the invention, the image processing system may re-divide the frame into new regions based on relative workloads experienced by the processing elements to evenly distribute workload. Furthermore, according to another embodiment of the invention, the image processing system may re-partition a spatial index based on relative workloads experienced by the processing elements to evenly distribute workload amongst workload managers.

Abstract: Systems and methods for balancing a load among multiple graphics processors that perform different portions of a rendering task. A rendering task is partitioned into portions for each of two (or more) graphics processors. The graphics processors perform their respective portions of the rendering task and return feedback data indicating completion of the assigned portion. Based on the feedback data, an imbalance can be detected between respective loads of two of the graphics processors. In the event that an imbalance exists, the rendering task is re-partitioned to increase the portion assigned to the less heavily loaded processor and to decrease the portion assigned to the more heavily loaded processor.