Abstract: Z testing during computer graphics rendering is performed in a manner so as to optimize rendering. The status of a pixel as non-promotable may be tracked using a pixel status array (PSA). Each PSA row may contain bits which correspond to the non-promotable status of pixels. Each row may include five pixels, the first four of which represent the pixels in a subspan. If the row corresponds to a valid subspan, a determination may be made as to whether any pixel in the subspan is represented by a one, indicating that the pixel is non-promotable. This row corresponds to a previous subspan that has been sent down rendering pipeline. If a one is present, then the current subspan may be stalled until the pixels of the previous subspan has gone through color calculation. If, in the row that has just been read, no pixels are represented by a one, then a determination may be made as to whether any pixels in the current subspan are non-promotable.

Abstract: An image generation apparatus provides interpolation and distortion correction. The interpolation and distortion correction may be provided in one or two dimensions. Nonlinear image scan trajectories, such as sinusoidal and bi-sinusoidal trajectories are accommodated. Horizontal and vertical scan positions are determined using a linear pixel clock, and displayed pixel intensities are determined using interpolation techniques.

Abstract: A tiled graphics memory permits graphics data to be stored in different tile formats. One application is selecting a tile format optimized for the data generated for particular graphical surfaces in different rendering modes. Consequently, the tile format can be selected to optimize memory access efficiency and/or packing efficiency. In one embodiment a first tile format stores pixel data in a format storing two different types of pixel data whereas a second tile format stores one type of pixel data. In one implementation, a z-only tile format is provided to store only z data but no stencil data. At least one other tile format is provided to store both z data and stencil data. In one implementation, z data and stencil data are stored in different portions of a tile to facilitate separate memory accesses of z and stencil data.

Abstract: There is provided an image processing device for controlling a display device to display a plurality of unit images making up a moving image at predetermined intervals, the image processing device including: 4×N (N: an arbitrary integer) quadrant memories; a separation section; a memory output control section; an assignment section; and an output control section.

Abstract: A method, in accordance with an embodiment of the invention, includes detecting a memory page miss associated with a thread operating on a Graphics Processing Unit (GPU). A request can be issued to receive the memory page associated with the memory page miss. There can be a switch into a runahead mode. During the runahead mode, a future memory page miss can be detected. During the runahead mode, a request can be issued to receive the future memory page associated with the future memory page miss.

Abstract: A raster operations (ROP) unit interleaves read and write requests for efficiently communicating with a frame buffer via a PCI Express (PCI E) link or other system bus that provides separate upstream and downstream data transfer paths. One example of a ROP unit processes pixels in groups, performing read modify writeback sequences for each group. The read requests associated with pixels in a second group are advantageously interleaved with the writeback requests for pixels in the first group prior to sending the requests on the system bus.

Abstract: A system including a first chip, a display controller and a copy device. The first chip includes a first memory. The display controller is configured to read a first frame from a second memory external to the first chip. The copy device is configured to copy the first frame from the second memory to the first memory while the display controller reads the first frame from the second memory. Subsequent to the copy device copying the first frame from the second memory to the first memory, the first frame is stored in both the first memory and the second memory.

Abstract: This disclosure describes techniques of loading batch commands into a graphics processing unit (GPU). As described herein, a GPU driver for the GPU identifies one or more graphics processing objects to be used by the GPU in order to render a batch of graphics primitives. The GPU driver may insert indexes associated with the identified graphics processing objects into a batch command. The GPU driver may then issue the batch command to the GPU. The GPU may use the indexes in the batch command to retrieve the graphics processing objects from memory. After retrieving the graphics processing objects from memory, the GPU may use the graphics processing objects to render the batch of graphics primitives.

Abstract: Methods for analyzing a list of routine identifiers to optimize processing of routines identified in the list. Some embodiments execute a set of routines in multiple passes where each pass comprises each routine in the set processing a single band of its source. The band size of the sources of the set is related to the size of a cache used during execution of the set. A band size of sources of the set is determined so that all data processed by and produced by any routine in the set can be stored to the cache while the routine processes one band of its source. Some embodiments use the list to combine two or more routines into a single routine where the list is modified accordingly. Some embodiments use the list for grouping and re-ordering routines identified in the list to send particular routines to an alternative processor for processing.

Abstract: For certain medical images, it is important and/or required that a user view all of a medical image at full resolution so that minute, but important, indicia in the medical image are not missed. A computing systems monitor the portions of the medical image that are displayed on the display device, notates those portions that have been displayed at full resolution (or other user-defined display parameters), and provides the user with information indicating portions that have not been viewed at full resolution and/or provides information indicating for which images of a multiple image examination full pixel display has been accomplished. The process reduces the possibility of missing an abnormality in a medical image due to the viewer not viewing a portion of the image at full resolution or using other user-defined display parameters.

Abstract: Rack Interface Pods can be augmented with non-KVM (keyboard, video and mouse) functionality that can enable greater analysis of the state of the computer to which the RIP is attached. A RIP can be augmented to include a non-KVM input connection (e.g., an Intelligent Platform/Chassis control protocol input) that is used to communicate between the server and the RIP. The RIP can then multiplex the received information with the KVM signals for transmission to a PEM or to an ARI port. Video and computer environment-style data can be multiplexed across a communications medium exiting the RIP such that they can be received by a remote computer.

Abstract: A computer architecture and programming model for high speed processing over broadband networks are provided. The architecture employs a consistent modular structure, a common computing module and uniform software cells. The common computing module includes a control processor, a plurality of processing units, a plurality of local memories from which the processing units process programs, a direct memory access controller and a shared main memory. A processing system for performing graphics processing is also provided. A first processor is of a first processor type and a number of second processors are of a second processor type. One of the second processors can perform graphics processing on a first set of graphics data to generate a second set of graphics data, and another of the second processors can perform graphics processing on the second set to generate a third set of graphics data.

Abstract: Provided are methods for managing texture data. The methods include preloading a first plurality of texture descriptor values from a memory location in a first buffer located in a first logic block, wherein the first buffer is further configured to receive data corresponding to non-texture functions performed in the first logic block and preloading the first plurality of texture descriptor values from a memory location into a second buffer in a second logic block if the first buffer is full. The methods further include utilizing the first plurality of texture descriptor values, within the second logic block, to perform a shader calculation, and loading, dynamically, a second plurality of texture descriptor values from memory into the first buffer, wherein the first logic block requires additional data. Additionally, the methods can include writing, if the first buffer is full, the second plurality of texture descriptor values over a portion of the first plurality of texture descriptor values.

Abstract: Systems and methods are disclosed for performing multiple processing of data in a network. In one embodiment, the network comprises a first display pipeline that is formed in real time from a plurality of possible display pipelines and that performs at least a first processing step on received data. A buffer stores the processed data and a second display pipeline that is formed in real time from a plurality of possible display pipelines performs at least a second processing step on stored data.

Abstract: A computer implemented method, apparatus, and computer usable program code for identifying differences in vector graphics files. A set of vector graphics file pairs are retrieved, wherein each vector graphics file pair in the set includes a first vector graphics file and a second vector graphics file. The first vector graphics file is compared with the second vector graphics file in each vector graphics file pair in the set using a one or more rules to form one or more comparisons. Differences are identified between the first and second vector graphics file in each vector graphics file pair in the set based on the comparisons. A merged file is created for each vector graphics file pair in the set containing differences from the comparisons to form results. The results are displayed in a graphical user interface after creating the merged file.

Abstract: A system and method are provided for dynamically selecting one or more modules of a graphics processor for processing content to support communication of the content over a wireless network link for subsequent display of the content utilizing a display.

Abstract: A system and method are provided including a first graphic processor in communication with a content source. In operation, the first graphics processor is adapted for processing content from the content source. Further included is a second graphics processor in communication with the first graphics processor utilizing a network. The second graphics processor is adapted for further processing the content for display purposes.

Abstract: A graphics system has virtual memory and a partitioned graphics memory that supports having an non-power of two number of dynamic random access memories (DRAMs). The graphics system utilizes page table entries to support addressing Tag RAMs used to store tag bits indicative of a compression status.

Abstract: A method of automatically tracking the portions of a 3D medical imaging volume, such as the voxels, that have already been displayed according to use-defined display parameters, notating those portions, and providing the user with information indicating what portions of the imaging volume have been displayed at full resolution.

Abstract: A system and method for processing graphics data which requires less read and write bandwidth. The graphics processing system includes an embedded memory array having at least three separate banks of single-ported memory in which graphics data are stored. A memory controller coupled to the banks of memory writes post-processed data to a first bank of memory while reading data from a second bank of memory. A synchronous graphics processing pipeline processes the data read from the second bank of memory and provides the post-processed graphics data to the memory controller to be written back to a bank of memory. The processing pipeline concurrently processes an amount of graphics data at least equal to that included in a page of memory. A third bank of memory is precharged concurrently with writing data to the first bank and reading data from the second bank in preparation for access when reading data from the second bank of memory is completed.