Abstract: Systems, methods, and computer readable media to encode and execute an indirect command buffer are described. A processor creates an indirect command buffer that is configured to be encoded into by a graphics processor at a later point in time. The processor encodes, within a command buffer, a produce command that references the indirect command buffer, where the produce command triggers execution on the graphics processor of a first operation that encodes a set of commands within the data structure. The processor also encodes, within the command buffer, a consume command that triggers execution on the graphics processor of a second operation that executes the set of commands encoded within the data structure. After encoding the command buffer, a processor commits the command buffer for execution on the graphics processor.

Abstract: Disclosed is a ray tracing device using MIMD based T&I scheduling, including: a ray receiving unit receiving a ray generated with respect to a specific frame according to a frame progress order and storing the received ray in a ray buffer; a ray scheduling unit allocating a ray provided by the ray buffer to one of a plurality of T&I pipelines, each of which including an input and output buffers; a traversal/intersection test performing unit performing a traversal/intersection test on an allocated ray in a parallel fashion by using each of the plurality of T&I pipelines and determining a triangle intersecting the allocated ray; and a test result ordering unit receiving information about the triangle from the plurality of T&I pipelines as a test result, storing the received test result in a test buffer, and re-arranging the received test result according to a frame progress order.

Abstract: In an example, an apparatus comprises a plurality of execution units; and logic, at least partially including hardware logic, to determine a sub-graph of a network that can be executed in a frequency domain and apply computations in the sub-graph in the frequency domain. Other embodiments are also disclosed and claimed.

Abstract: An electronic device includes: a display driver integrated circuit (IC) configured to transmit image data to a display; and a host coupled to the display driver IC through a first interface and a second interface, wherein the host is configured to transmit the image data to the display driver IC through the first interface and transmit a mode switching signal to the display driver IC through the second interface, wherein the mode switching signal indicates whether the image data is to be transmitted in a command mode or in a video mode.

Abstract: A computing system includes a base processing device, as well as a display device having a screen. In an attached mode, the base processing device is mechanically attached to the base processing device, and is to display a user interface on the display device using a mechanical data connection between the base processing device and the display device. In a detached mode, the base processing device is mechanically detached from the display device, and is to render the user interface and transmit the rendered user interface to the display device over a wireless data connection between the base processing device and the display device. The display device is to receive and responsively display the rendered user interface.

Abstract: A warp processing unit controls, in dependence on a warp program counter shared between a plurality of threads processing respective graphics fragments, fetching of a next instruction to be executed for at least some of the plurality of threads. In response to a determination that a given subset of threads is to be discarded when at least one other subset of threads is to continue, the warp processing unit processes the given subset of threads in a discarded state. For a thread processed in the discarded state, execution of instructions continues for the discarded thread, and at least one of: generation of data access messages triggered by the discarded thread is suppressed; and at least one processing operation, which would be deferred until completion of the discarded thread had the thread not been discarded, is enabled to be commenced independently of an outcome of the discarded thread.

Abstract: Embodiments of the present disclosure relate to a configurable convolution engine that receives configuration information to perform convolution or its variant operations on streaming input data of various formats. To process streaming input data, input data of multiple channels are received and stored in an input buffer circuit in an interleaved manner. Data values of the interleaved input data are retrieved and forwarded to multiplier circuits where multiplication with a corresponding filter element of a kernel is performed. Varying number of kernels with different sizes and sparsity can also be used for the convolution operations.

Abstract: Disclosed is a hardware controller of a Nand device, a control method and a liquid crystal display. The hardware controller includes: a bad block management module, configured to manage bad block information of the Nand device, where the bad block information represents a bad block set in the Nand device; a main control module, configured to receive an operation command of a terminal; wherein the operation command is used to indicate a read/write operation on a target block set of the Nand device and a data transmission mode to perform the read/write operation, and the data transmission mode includes at least one of parallel transmission and serial transmission; and a read/write module, configured to skip a block in the Nand device that exists both in the bad block set and the target block set, and perform the read/write operation on remaining blocks in the target block set.

Abstract: An image processor is described. The image processor includes an I/O unit to read input image data from external memory for processing by the image processor and to write output image data from the image processor into the external memory. The I/O unit includes multiple logical channel units. Each logical channel unit is to form a logical channel between the external memory and a respective producing or consuming component within the image processor. Each logical channel unit is designed to utilize reformatting circuitry and addressing circuitry. The addressing circuitry is to control addressing schemes applied to the external memory and reformatting of image data between external memory and the respective producing or consuming component. The reformatting circuitry is to perform the reformatting.

Abstract: Methods, systems, and computer-readable media for capacity reservation for virtualized graphics processing are disclosed. A request is received to attach a virtual GPU to a virtual compute instance. The request comprises one or more constraints. Availability information is retrieved from a data store that indicates virtual GPUs available in a provider network and matching the one or more constraints. A virtual GPU is selected from among the available virtual GPUs in the availability information. The selected virtual GPU is reserved for attachment to the virtual compute instance. The virtual compute instance is implemented using CPU resources and memory resources of a physical compute instance, the virtual GPU is implemented using a physical GPU in the provider network, and the physical GPU is accessible to the physical compute instance over a network.

Abstract: A GPU comprises: a GPR comprising registers; an L1 cache coupled to the GPR and configured to implement a pixel mapping by: segregating pixels of an image into regions, the regions comprise a first region and a second region, the first region comprises first pixels, and the second region comprises second pixels, loading the first pixels into the GPR in a horizontal manner, and loading the second pixels into the GPR in a vertical manner; and an ALU configured to read the first pixels and the second pixels independently of a shared memory.

Abstract: An example head-worn device includes a camera, a display device, weld detection circuitry, and pixel data processing circuitry. The camera generates first pixel data from a field of view of the head-worn device. The display device displays second pixel data to a wearer of the head-worn device based on the first pixel data captured by the camera. The weld detection circuitry determines whether a welding arc is present and generates a control signal indicating a result of the determination. The pixel data processing circuitry processes the first pixel data captured by the camera to generate the second pixel data for display on the display device, where a mode of operation of said pixel data processing circuitry is selected from a plurality of modes based on said control signal.

Abstract: When a shader program is to be executed by a graphics processor, the graphics processor is caused to execute at least two variants of the shader program and the operation of the graphics processor when executing execution threads for the different variants of the shader program is monitored. A variant of the shader program to be executed by subsequent execution threads that are to execute the shader program is then selected based on the monitoring of the operation of the shading stage when executing the execution threads for the different variants of the shader program.

Abstract: An apparatus to facilitate processing of a sparse matrix is disclosed. The apparatus includes a plurality of processing units each comprising one or more processing elements, including logic to read operands, a multiplication unit to multiply two or more operands and a scheduler to identify operands having a zero value and prevent scheduling of the operands having the zero value at the multiplication unit.

Abstract: Embodiments are disclosed for inserting profiling instructions into graphics processing unit (GPU) kernels. An example apparatus includes an entry point detector to detect a first entry point address and a second entry point address of an original GPU kernel. An instruction inserter is to create a corresponding instrumented GPU kernel from the original GPU kernel by adding instructions of the original GPU kernel and one or more profiling instructions to the instrumented GPU kernel. The instruction inserter is to insert, at the first entry point address of the instrumented GPU kernel, a first jump instruction to jump to first profiling initialization instructions, the instruction inserter to insert, at the second entry point address of the instrumented GPU kernel, a second jump instruction to jump to second profiling initialization instructions. The instruction inserter is to insert profiling measurement instructions of the profiling instructions into the instrumented GPU kernel.

Abstract: A display apparatus, which outputs a representation of content data, includes a communicator that obtains from a content distribution apparatus the content data and robot operation data used for operating a robotic device, a storage that stores the content data and the robot operation data, and a controller that transmits the robot operation data to the robotic device connected the display apparatus when the display apparatus outputs the representation of the content data.

Abstract: Embodiments described herein provide a graphics processor in which dependency tracking hardware is simplified via the use of compiler provided software scoreboard information. In one embodiment the shader compiler for shader programs is configured to encode software scoreboard information into each instruction. Dependencies can be evaluated by the shader compiler and provided as scoreboard information with each instruction. The hardware can then use the provided information when scheduling instructions. In one embodiment, a software scoreboard synchronization instruction is provided to facilitate software dependency handling within a shader program. Using software to facilitate software dependency handling and synchronization can simplify hardware design, reducing the area consumed by the hardware. In one embodiment, dependencies can be evaluated by the shader compiler instead of the GPU hardware.

Abstract: A method is described. The method includes simulating execution of an image processing application software program. The simulating includes intercepting kernel-to-kernel communications with simulated line buffer memories that store and forward lines of image data communicated from models of producing kernels to models of consuming kernels. The simulating further includes tracking respective amounts of image data stored in the respective line buffer memories over a simulation runtime. The method also includes determining respective hardware memory allocations for corresponding hardware line buffer memories from the tracked respective amounts of image data. The method also includes generating configuration information for an image processor to execute the image processing application software program. The configuration information describes the hardware memory allocations for the hardware line buffer memories of the image processor.

Abstract: A graphics processing method is provided, adapted to a graphic processing unit, the steps including: receiving, via a CSP, a first command associated with all render targets from a display driver; determining, via the display driver, sizes and areas of a plurality of tiles in each frame; repeatedly controlling, via a scissor pool unit, a graphics processing unit to perform drawing processing for each tile according to the first command; comparing, via a signature comparing unit of a cache memory, a signature of a current tile of a current frame and a signature of a tile corresponding to the same position of a previous frame and generating a comparison result; and determining whether to flush the dirty data of the current tile stored in the cache memory from the cache memory to a memory access unit according to the comparison result.

Abstract: A method for processing images, including: determining, subsequent to transmitting content of a target image corresponding to a current processing request to a processor, whether the target image is being used by other processing requests; and in response to the determination that the target image is not being used by the other processing requests, releasing memory utilized by the target image at a target memory, the target memory being used to store a copy corresponding to the target image.