Abstract: A graphics processing unit (GPU) instructs a display control module to capture content and display captured content in response to the refresh rate of a display exceeding a frame generation rate of the GPU. Rather than re-transmit the same frame multiple times, the GPU instructs the display control module to replay a previously-transmitted frame. During a refresh cycle in which the display control module is replaying captured content, the GPU omits accessing memory to retrieve and resend the frame that is being replayed, and instead sends only invalid data and GPU timing information so that the display control module remains synchronized with the GPU.

Abstract: A computing device includes one or more processors, random access memory (RAM), and a non-transitory computer-readable storage medium storing instructions for execution by the one or more processors. The computing device receives first data and classifies the first data using a neural network that includes at least one quantized layer. The classifying includes reading values from the random access memory for a set of weights of the at least one quantized layer of the neural network using first read parameters corresponding to a first error rate.

Abstract: Systems and methods are disclosed for calculating dynamic ambient occlusion (AO) values for character models to yield high-quality approximations of global illumination effects. The approach utilizes a dual component machine-learning model that factorizes dynamic AO computation into a non-linear component, in which visibility is determined by approximating spheres and their casted shadows, and a linear component that leverages a skinning-like algorithm for efficiency. The parameters of both components are trained in a regression against ground-truth AO values. The resulting model accommodates lighting interactions with external objects and can be generalized without requiring carefully constructed training data.

Abstract: The disclosure discloses a reconfigurable hardware acceleration method and system for Gaussian pyramid construction and belongs to the field of hardware accelerator design. The system provided by the disclosure includes a static random access memory (SRAM) bank, a first in first out (FIFO) group, a switch network, a shift register array, an adder tree module, a demultiplexer, a reconfigurable PE array, and a Gaussian difference module. In the disclosure, according to the requirements of different scenarios and different tasks for the system, reconfigurable PE array resources can be configured to realize convolution calculations of different scales. The disclosure includes methods of fast and slow dual clock domain design, dynamic edge padding design, and input image partial sum reusing design.

Abstract: A method includes simulating a process, with computer-based software, to produce virtual data about the process; identifying process parameters for a real-world version of the process; providing a real-world sensor to sense a parameter associated with the real-world version of the process; receiving sensor readings from the real-world sensor while the real-world version is being performed; and training a machine-learning software model to predict a behavior of the real-world sensor based on the virtual data about the process, the process parameters, and the sensor readings.

Abstract: Systems, apparatuses and methods may provide for technology that generates, by a first neural network, an initial set of model weights based on input data and iteratively generates, by a second neural network, an updated set of model weights based on residual data associated with the initial set of model weights and the input data. Additionally, the technology may output a geometric model of the input data based on the updated set of model weights. In one example, the first neural network and the second neural network reduce the dependence of the geometric model on the number of data points in the input data.

Abstract: Apparatuses, methods, and computer program products for safety compliance determinations are provided. An example method includes receiving three-dimensional (3D) image data indicative of a field of view of a 3D imager that includes a first user upon which to perform a compliance determination. The method further includes generating a fit parameter associated with a safety device of the first user within the field of view of the 3D imager based upon the 3D image data, the fit parameter indicative of an associated positioning of the safety device relative to the first user. The method also includes comparing the fit parameter with a compliance threshold associated with the safety device and generating an alert signal in an instance in which the fit parameter fails to satisfy the compliance threshold. In some instances, the method may supply the 3D image data to an artificial neural network to generate the fit parameter.

Abstract: Techniques to improve performance of matrix multiply operations are described in which a compute kernel can specify one or more element-wise operations to perform on output of the compute kernel before the output is transferred to higher levels of a processor memory hierarchy.

Abstract: A processing apparatus is described. The apparatus includes a plurality of processing cores, including a first processing core and a second processing core a first field programmable gate array (FPGA) coupled to the first processing core to accelerate execution of graphics workloads processed at the first processing core and a second FPGA coupled to the second processing core to accelerate execution of workloads processed at the second processing core.

Abstract: The present disclosure relates to methods and apparatus for mapping a source location of input data for processing by a graphics processing unit. The apparatus can configure a processing element of the graphics processing unit with a predefined rule for decoding a data source parameter for executing a task by the graphics processing unit. Moreover, the apparatus can store the parameter in local storage of the processing element and configure the processing element to decode the parameter according to the at least one predefined rule to determine a source location of the input data and at least one relationship between invocations of the task. The apparatus can also load, to the local storage of the processing element, the input data from a plurality of memory addresses of the source location determined by the parameter. A one logic unit can then execute the task on the loaded input data.

Abstract: A neural processor. In some embodiments, the processor includes a first tile, a second tile, a memory, and a bus. The bus may be connected to the memory, the first tile, and the second tile. The first tile may include: a first weight register, a second weight register, an activations buffer, a first multiplier, and a second multiplier. The activations buffer may be configured to include: a first queue connected to the first multiplier and a second queue connected to the second multiplier. The first queue may include a first register and a second register adjacent to the first register, the first register being an output register of the first queue. The first tile may be configured: in a first state: to multiply, in the first multiplier, a first weight by an activation from the output register of the first queue, and in a second state: to multiply, in the first multiplier, the first weight by an activation from the second register of the first queue.

Abstract: A neural processor. In some embodiments, the processor includes a first tile, a second tile, a memory, and a bus. The bus may be connected to the memory, the first tile, and the second tile. The first tile may include: a first weight register, a second weight register, an activations buffer, a first multiplier, and a second multiplier. The activations buffer may be configured to include: a first queue connected to the first multiplier and a second queue connected to the second multiplier. The first queue may include a first register and a second register adjacent to the first register, the first register being an output register of the first queue. The first tile may be configured: in a first state: to multiply, in the first multiplier, a first weight by an activation from the output register of the first queue, and in a second state: to multiply, in the first multiplier, the first weight by an activation from the second register of the first queue.

Abstract: A neural processor. In some embodiments, the processor includes a first tile, a second tile, a memory, and a bus. The bus may be connected to the memory, the first tile, and the second tile. The first tile may include: a first weight register, a second weight register, an activations buffer, a first multiplier, and a second multiplier. The activations buffer may be configured to include: a first queue connected to the first multiplier and a second queue connected to the second multiplier. The first queue may include a first register and a second register adjacent to the first register, the first register being an output register of the first queue. The first tile may be configured: in a first state: to multiply, in the first multiplier, a first weight by an activation from the output register of the first queue, and in a second state: to multiply, in the first multiplier, the first weight by an activation from the second register of the first queue.

Abstract: Embodiments are disclosed for inserting profiling instructions into graphics processing unit (GPU) kernels. An example apparatus includes instructions, and at least one processor to execute the instructions to determine whether a GPU supports modification of entry point addresses, detect a first entry point address and a second entry point address of an original GPU kernel, create a corresponding instrumented GPU kernel from the original GPU kernel based on the determination by inserting at least one of first profiling initialization instructions or first jump instructions at the first entry point address of the instrumented GPU kernel, inserting at least one of second profiling initialization instructions or second jump instructions at the second entry point address of the instrumented GPU kernel, and inserting profiling measurement instructions into the instrumented GPU kernel.

Abstract: A neural processor. In some embodiments, the processor includes a first tile, a second tile, a memory, and a bus. The bus may be connected to the memory, the first tile, and the second tile. The first tile may include: a first weight register, a second weight register, an activations buffer, a first multiplier, and a second multiplier. The activations buffer may be configured to include: a first queue connected to the first multiplier and a second queue connected to the second multiplier. The first queue may include a first register and a second register adjacent to the first register, the first register being an output register of the first queue. The first tile may be configured: in a first state: to multiply, in the first multiplier, a first weight by an activation from the output register of the first queue, and in a second state: to multiply, in the first multiplier, the first weight by an activation from the second register of the first queue.

Abstract: Content data of a display target is acquired in accordance with a user's operations and is used to determine a configuration of a display image. Of the regions to be rendered using fonts in the display image, the region in which a character is to be displaced by a very small amount is determined. The characters targeted for displacement are rendered while being displaced over time in accordance with predetermined displacement rules. The characters not targeted for displacement are rendered in a reference position. With all characters rendered, the display image is completed and output. The processes of S12 to S24 are repeated until display is terminated.

Abstract: An apparatus to facilitate thread scheduling is disclosed. The apparatus includes logic to store barrier usage data based on a magnitude of barrier messages in an application kernel and a scheduler to schedule execution of threads across a plurality of multiprocessors based on the barrier usage data.

Abstract: A product visualization and manufacturing system and method which bridges two-dimensional (2D) and three-dimensional (3D) technologies in order to quickly and effectively display the product. The system and methods are helpful for many different product types, but especially for custom-designed jewelry products. The 2D/3D bridging invention enables a user to generate a three-dimensional generic base model of a product, modify the three-dimensional generic base model using two-dimensional image manipulation, and display a three-dimensional customized base model of a customized product. Templates, material libraries, HDRI maps, and lighting schemes may be employed.

Abstract: A combustion simulation system is provided. The combustion simulation system can be performed using a computing device operated by a computer user or artist. The computer-implemented method of generating one or more visual representations of a combustion even is provided. The method includes simulating the combustion event, which transforms combustion reactants into combustion products, the combustion event occurring at a reference pressure, automatically determining values of combustion properties, the values of the combustion properties being calculated as a function of a nonzero pressure field, and generating the one or more visual representations of the combustion event based on the values of combustion properties.

Abstract: A computer system is provided for converting images through use of a trained neural network. A source image is divided into blocks and context data is added to each pixel block. The context blocks are split into channels and each channel from the same context block is added to the same activation matrix. The action matrix is then executed against a trained neural network to produce a changed activation matrix. The changed activation matrix is then used to generate a converted image.