Abstract: An embodiment for adjusting digital content in a flexible display device is provided. The embodiment may include receiving data relating to a position and orientation of a reference device relative to a user. The embodiment may also include identifying an orientation of a display surface of a mobile device and a relative position of the mobile device relative to a viewing direction of the user. The embodiment may further include identifying an optimal viewing angle of display content on the display surface of the mobile device. The embodiment may also include in response to determining the display content is not able to be displayed as a hologram, aligning the display content as text based on the optimal viewing angle. The embodiment may further include presenting the aligned display content as text to the user.

Abstract: An artificial neural network (ANN) generates a base expanded matrix that represents an output of a layer of the ANN, such as the output layer. Values in each row are grouped with respect to a set of network parameters in a previous layer, and a sum of the values in each row produces an output vector of activations. The ANN updates the values in at least one column of the expanded matrix according to parameter updates, which results in an updated expanded matrix or an update expanded matrix. An error or a total cost can be computed from the updated expanded matrix or the update expanded matrix. Nonlinear activation functions can be modeled as piecewise linear functions, and a change in an activation function's slope can be modeled as a linear update to an expanded matrix. Parameter updates can be constrained to a restricted value set in order to simplify update operations performed on the expanded matrices.

Abstract: An apparatus to facilitate processing of a sparse matrix for arbitrary graph data is disclosed. The apparatus includes a graphics processing unit having a data management unit (DMU) that includes a scheduler for scheduling matrix operations, an active logic for tracking active input operands, and a skip logic for tracking unimportant input operands to be skipped by the scheduler. Processing circuitry is coupled to the DMU. The processing circuitry comprises a plurality of processing elements including logic to read operands and a multiplication unit to multiply two or more operands for the arbitrary graph data.

Abstract: A processor includes a register, a non-zero weight value selector and a multiplier. The register holds a first group of weight values and a second group of weight values. Each group of weight values includes at least one weight value, and each weight value in the first group of weight values corresponding to a weight value in the second group of weight values. The non-zero weight value selector selects a non-zero weight value from a weight value in the first group of weight values or a non-zero weight value in the second group of weight values that corresponds to the weight value in the first group of weight values. The multiplier multiplies the selected non-zero weight value and an activation value that corresponds to the selected non-zero weight value to form an output product value.

Abstract: A novel and useful system and method of improved power performance and lowered memory requirements for an artificial neural network based on packing memory utilizing several structured sparsity mechanisms. The invention applies to neural network (NN) processing engines adapted to implement mechanisms to search for structured sparsity in weights and activations, resulting in a considerably reduced memory usage. The sparsity guided training mechanism synthesizes and generates structured sparsity weights. A compiler mechanism within a software development kit (SDK), manipulates structured weight domain sparsity to generate a sparse set of static weights for the NN. The structured sparsity static weights are loaded into the NN after compilation and utilized by both the structured weight domain sparsity mechanism and the structured activation domain sparsity mechanism.

Abstract: Provided are a method and an apparatus for performing scalable video decoding, wherein the method and the apparatus down-sample input video, determine the down-sampled input video as base layer video, generate prediction video for enhancement layer video by applying an up-scaling filter to the base layer video, and code the base layer video and the prediction video, wherein the up-scaling filter is a convolution filter of a deep neural network.

Abstract: A method of processing a workload in a graphics processing unit (GPU) may include detecting a work item of the workload in the GPU, determining a cache policy for the work item, and operating at least a portion of a cache memory hierarchy in the GPU for at least a portion of the work item based on the cache policy. The work item may be detected based on information received from an application and/or monitoring one or more performance counters by a driver and/or hardware detection logic. The method may further include monitoring one or more performance counters, wherein the cache policy for the work item may be determined and/or changed based on the one or more performance counters. The cache policy for the work item may be selected based on a runtime learning model.

Abstract: A networked system includes an application that produces application frames at a first application frame rate, a graphics processing system that processes the application frames to produce graphics frames at a first graphics frame rate, a VDI system that processes the graphics frames to produce VDI frames at a first VDI frame rate, and an endpoint device that processes the VDI frames to produce endpoint frames at an endpoint frame rate. A frame rate optimization system monitors the application processing, the graphics processing, the VDI processing, and the endpoint processing and, based on the endpoint frame rate, reconfigures at least one of: the application to produce the application frames at a second application frame rate, the graphics processing system to produce the graphics frames at a second graphics frame rate, or the VDI system to produce the VDI frames at a second VDI frame rate.

Abstract: In an example, an apparatus comprises a plurality of execution units; and logic, at least partially including hardware logic, to determine a sub-graph of a network that can be executed in a frequency domain and apply computations in the sub-graph in the frequency domain. Other embodiments are also disclosed and claimed.

Abstract: A method for augmented reality content production based on attribute information application according to an embodiment of the present disclosure, as a method for augmented reality content production based on attribute information application by a production application executed by at least one or more processors of a computing device, comprises providing a virtual object authoring space which is a virtual space for authoring a virtual object and includes at least one or more reference objects; providing a virtual object authoring interface for the virtual object authoring space; generating augmentation relationship attribute information based on a virtual object generated based on the provided virtual object authoring interface and at least one reference object of the virtual object authoring space; storing the virtual object by including the generated augmentation relationship attribute information; and displaying the stored virtual object on a reference object in a different space other than the virtual ob

Abstract: An embodiment method for converting an initial digital image into a converted digital image, electronic chip, system and computer program product are disclosed, the initial digital image comprising a set of pixels, the pixels being associated respectively with colors, the initial digital image being acquired by an acquisition device, and the converted digital image able to be used by a neural network. The embodiment method comprises redimensioning of the initial digital image in order to obtain an intermediate digital image, the redimensioning being carried out by a reduction in the number of pixels of the initial image, modification of a format of one of the pixels of the intermediate digital image in order to obtain a converted digital image, the modification being carried out, after the redimensioning, by increasing the number of bits used to represent the color of the pixel.

Abstract: A transceiver system includes a transmitter including a first driving signal output unit and a second driving signal output unit and a receiver including a first sensing signal input unit and a second sensing signal input unit. A first channel includes a first input/output line and a second input/output line that connect the first driving signal output unit and the first sensing signal input unit, and are configured to transfer signals having different phases; a second channel including a third input/output line and a fourth input/output line that connect the second driving signal output unit and the second sensing signal input unit, and are configured to transfer signals having different phases; and a first compensation capacitor including a first electrode electrically connected to the second input/output line and a second electrode electrically connected to the third input/output line.

Abstract: A computing device includes one or more processors, random access memory (RAM), and a non-transitory computer-readable storage medium storing instructions for execution by the one or more processors. The computing device receives first data and classifies the first data using a neural network that includes at least one quantized layer. The classifying includes reading values from the random access memory for a set of weights of the at least one quantized layer of the neural network using first read parameters corresponding to a first error rate.

Abstract: An aspect provides a computer-implemented method for compiling software code. The method comprises: receiving software code to compile; receiving a set of parameters associated with settings and software employed to compile the software code; forming a first hash of the set of parameters to establish a unique identification of the set of parameters used to compile the software code; and associating the first hash with the compiled code. A further aspect provides a computer-implemented method of checking compatibility of compiled software code.

Abstract: A graphics pipeline includes a cache having cache lines that are configured to store data used to process frames in a graphics pipeline. The graphics pipeline is implemented using a processor that processes frames for the graphics pipeline using data stored in the cache. The processor processes a first frame and writes back a dirty cache line from the cache to a memory concurrently with processing of the first frame. The dirty cache line is retained in the cache and marked as clean subsequent to being written back to the memory. In some cases, the processor generates a hint that indicates a priority for writing back the dirty cache line based on a read command occupancy at a system memory controller.

Abstract: Methods, systems, and computer-storage media fare provided for utilizing a GPU for user-defined image compositing operations. A sequence of compositing operations is determined for a graphical image document based on at least one user-defined layer property such as a layer mode or an opacity level. A domain-specific language runtime, such as Halide runtime, is used to provide encoded objects for each operation within the sequence with the code being optimized for the GPU platform. A command buffer with a plurality of commands comprising the encoded operations is created and committed to the GPU for execution of the compositing operations. Commands are committed to the GPU in an asynchronous nature such that additional command buffers may be created and committed the GPU prior to receiving a response from the GPU on an earlier command buffer.

Abstract: A processor includes a register, a non-zero weight value selector and a multiplier. The register holds a first group of weight values and a second group of weight values. Each group of weight values includes at least one weight value, and each weight value in the first group of weight values corresponding to a weight value in the second group of weight values. The non-zero weight value selector selects a non-zero weight value from a weight value in the first group of weight values or a non-zero weight value in the second group of weight values that corresponds to the weight value in the first group of weight values. The multiplier multiplies the selected non-zero weight value and an activation value that corresponds to the selected non-zero weight value to form an output product value.

Abstract: The present disclosure relates to systems, methods, and non-transitory computer readable media for generating a modified digital image from extracted spatial and global codes. For example, the disclosed systems can utilize a global and spatial autoencoder to extract spatial codes and global codes from digital images. The disclosed systems can further utilize the global and spatial autoencoder to generate a modified digital image by combining extracted spatial and global codes in various ways for various applications such as style swapping, style blending, and attribute editing.

Abstract: Systems and methods are provided for implementing hardware optimization for a hardware accelerator. The hardware accelerator emulates a neural network. Training of the neural network integrates a regularized pruning technique to systematically reduce a number of weights. A crossbar array included in hardware accelerator can be programmed to calculate node values of the pruned neural network to selectively reduce the number of weight column lines in the crossbar array. During deployment, the hardware accelerator can be programmed to power off periphery circuit elements that correspond to a pruned weight column line to optimize the hardware accelerator for power. Alternatively, before deployment, the hardware accelerator can be optimized for area by including a finite number of weight column line. Then, regularized pruning of the neural network selectively reduces the number of weights for consistency with the finite number of weight columns lines in the hardware accelerator.

Abstract: Systems and methods are disclosed for aligning a two-dimensional (2D) design image to a 2D projection image of a three-dimensional (3D) design model. One method comprises receiving a 2D design document, the 2D design document comprising a 2D design image, and receiving a 3D design file comprising a 3D design model, the 3D design model comprising one or more design elements. The method further comprises generating a 2D projection image based on the 3D design model, the 2D projection image comprising a representation of at least a portion of the one or more design elements, generating a projection barcode based on the 2D projection image, and generating a drawing barcode based on the 2D design image. The method further comprises aligning the 2D projection image and the 2D design image by comparing the projection barcode and the drawing barcode.