Abstract: Disclosed herein are methods and systems for improving GPU processing during visualization operations. In one embodiment, the method comprises receiving a data frame at a central processing unit (CPU), the data frame including a plurality of pieces of associated data; identifying, by the CPU, feature information corresponding to the plurality of pieces of associated data; generating, by the CPU, overall feature information by combining at least a portion of the feature information; and sending, by the CPU, the overall feature information to a graphics processing unit (GPU).

Abstract: Methods, apparatus, and machine-readable mediums are described for doing predictive content branch selection for rendering environments such as virtual reality systems. User data is aggregated from multiple users. Each user is classified based upon the user data. Personalization parameters are identified for each of the plurality of users. Content to be presented is determined and modified with a modification for a user based upon the personalization parameters for the user. The modified content is sent to the user.

Abstract: A graphics processing system processes primitive fragments using a rendering space which is sub-divided into tiles. The graphics processing system comprises processing engines configured to apply texturing and/or shading to primitive fragments. The graphics processing system also comprises a cache system for storing graphics data for primitive fragments, the cache system including multiple cache subsystems. Each of the cache subsystems is coupled to a respective set of one or more processing engines. The graphics processing system also comprises a tile allocation unit which operates in one or more allocation modes to allocate tiles to processing engines. The allocation mode(s) include a spatial allocation mode in which groups of spatially adjacent tiles are allocated to the processing engines according to a spatial allocation scheme, which ensures that each of the groups of spatially adjacent tiles is allocated to a set of processing engines which are coupled to the same cache subsystem.

Abstract: Disclosed herein is a processor for deep learning. In one embodiment, the processor comprises: a load and store unit configured to load and store image pixel data and stencil data; a register unit, implementing a banked register file, configured to: load and store a subset of the image pixel data from the load and store unit, and concurrently provide access to image pixel values stored in a register file entry of the banked register file, wherein the subset of the image pixel data comprises the image pixel values stored in the register file entry; and a plurality of arithmetic logic units configured to concurrently perform one or more operations on the image pixel values stored in the register file entry and corresponding stencil data of the stencil data.

Abstract: A system, method, and apparatus provide an improvement to image rendering and the computing resources used to render processing intensive image objects. Exemplary embodiments receive an image object and depending on the type of image object, the image object size, or complexity, a determination is made as to whether the image object should be divided up and processed using multiple threads with a multi-core computer processor. When multiple threads are used, a different thread is assigned to each section of the divided-up image object. Each section may then be processed by its respective thread until converted and mapped into an output image space that yields a final rendered image.

Abstract: There are provided a display structure, a display method, a display device and an operating system. The display structure includes: a first display buffer configured to store a first user display interface; a second display buffer configured to store a second user display interface; and a display cache, the second user display interface is a user display interface that is obtained by processing the first user display interface and has a resolution conforming to a resolution of the display cache.

Abstract: Described herein is a method for allocating resources for rendering. The method can include assembling a plurality of render nodes. The render nodes can have their defined input(s) and output(s). From the assembled set of render nodes a schedule can be compiled. The compiled schedule for the plurality of rendering nodes can be based at least on the defined input(s) and output(s). Additionally, the plurality of rendering nodes can be scheduled such that more than one rendering algorithm can be carried out at a point in time. Within the compiling, a set of resource barriers can be defined. The set of resource barriers can include system resource barriers. These system resource barriers can be for processing the set of render nodes based on the created schedule.

Abstract: In an example, an apparatus comprises a plurality of execution units; and logic, at least partially including hardware logic, to determine a sub-graph of a network that can be executed in a frequency domain and apply computations in the sub-graph in the frequency domain. Other embodiments are also disclosed and claimed.

Abstract: Described herein is a method for allocating resources of a graphics processing unit (GPU). Methods as described herein can include assembling a plurality of work nodes having defined inputs and outputs, wherein at least one work node is a rendering work node and at least one work node is a compute work node. A schedule can be created for the plurality of work nodes based at least on the defined inputs and outputs, wherein the plurality of work nodes can be scheduled such that more than one GPU process can be carried out at a point in time. Additionally, the schedule can be created such that both render nodes and compute nodes can use the same GPU resources either simultaneously or at separate times. For example, the GPU does not need to be partitioned where certain resources are only for compute processes and others are reserved for rendering processes. A set of system resource barriers can be determined for processing the set of work nodes based on the created schedule.

Abstract: Embodiments described herein provide techniques enable a compute unit to continue processing operations when all dispatched threads are blocked. One embodiment provides for an apparatus comprising a thread dispatcher to dispatch a thread for execution; a compute unit having a single instruction, multiple thread architecture, the compute unit to execute multiple concurrent threads; and a memory coupled with the compute unit, the memory to store thread state for a suspended thread, wherein the compute unit is to: detect that all threads on the compute unit are blocked from execution, select a victim thread from the multiple concurrent threads, suspend the victim thread, store thread state of the victim thread to the memory, and replace the victim thread with an additional thread to be executed.

Abstract: Processing of non-real-time and real-time workloads is performed using discrete pipelines. A first pipeline includes a first shader and one or more fixed function hardware blocks. A second pipeline includes a second shader that is configured to emulate the at least one fixed function hardware block. First and second memory elements store first state information for the first pipeline and second state information for the second pipeline, respectively. A non-real-time workload executing in the first pipeline is preempted at a primitive boundary in response to a real-time workload being dispatched for execution in the second pipeline. The first memory element retains the first state information in response to preemption of the non-real-time workload. The first pipeline is configured to resume processing the subsequent primitive on the basis of the first state information stored in the first memory element.

Abstract: A computer-implemented method is provided for estimating the performance of a GPU application on a new computing machine having an increased GPU-link performance ratio relative to a current computing machine having a current GPU-link performance ratio. The method includes adding a delay to CPU-GPU communication on the current computing machine to simulate a delayed-communication environment on the current computing machine. The method further includes executing the target GPU application in the delayed-communication environment. The method also includes measuring the performance of the target GPU application in the delayed-communication environment. The method additionally includes estimating the performance of the new computing machine having the increased higher GPU-link performance ratio, based on the measured performance of the target GPU application in the delayed-communication environment.

Abstract: A computer system to continuously maintain a user session when a display device is mechanically connected and disconnected with a base processing device is described. The computer system allows the user to run applications during the user session on the base processing device and use the display device as a monitor. The display device can be detached from the base processing device, and the base processing device can continue running the applications for the user session. In this mode, the separated display device can be used as a tablet form factor computing device which can accept user input and send the user input to the base processing device. Among other functions, the base processing device can operate with the display device disconnected by generating session content for the display device, including, for example, sending application content, video streams, and other content to the display device.

Abstract: An apparatus to facilitate pixel compression is disclosed. The apparatus includes a rasterizer module to convert an image to a plurality of pixels, an interface coupled to the rasterizer module, a depth check module coupled to the interface and compression logic to perform a compression encoding on the plurality of pixels, including dividing the plurality of pixels into a mega pixel block having a plurality of pixel blocks, determining coverage information for pixels in each of the plurality of pixel blocks, encoding each of the plurality of pixel blocks based on the coverage information to generate a mega encoded block.

Abstract: A method is described. The method includes simulating execution of an image processing application software program. The simulating includes intercepting kernel-to-kernel communications with simulated line buffer memories that store and forward lines of image data communicated from models of producing kernels to models of consuming kernels. The simulating further includes tracking respective amounts of image data stored in the respective line buffer memories over a simulation runtime. The method also includes determining respective hardware memory allocations for corresponding hardware line buffer memories from the tracked respective amounts of image data. The method also includes generating configuration information for an image processor to execute the image processing application software program. The configuration information describes the hardware memory allocations for the hardware line buffer memories of the image processor.

Abstract: A data processing system replicates the operation of a target graphics processor using a graphics processor of the data processing system. A driver for the target graphics processor converts higher level commands and program expressions intended for the target graphics processor into lower level control data and instructions suitable for use by the target graphics processor. The lower level control data and instructions suitable for use by the target graphics processor are then converted into lower level control data and instructions for the graphics processor of the data processing system. The graphics processor of the data processing system then generates an output using the lower level control data and instructions for the graphics processor of the data processing system. The data processing system provides an efficient and comprehensive testing environment when replicating the operation of the target graphics processor.

Abstract: Graphics processing systems and methods are described. A graphics processing apparatus may comprise one or more graphics processing cores, a shared buffer accessible to a user mode driver (UMD) associated with an application in an unprivileged domain, the UMD to write one or more commands to the shared buffer, and a controller parse a workload in the shared buffer to identify one or more commands in the workload, the workload added by the application executing in the unprivileged domain, associate a trigger with a command in the workload, transfer the workload to one or more components of the graphics processing apparatus for execution, and upon execution of the command associated with the trigger, sample the shared buffer to identify a new workload added to the shared buffer. The one or more components of the graphics processing apparatus automatically execute the new workload added to the shared buffer.

Abstract: An apparatus and method for performing screen captures on display devices are disclosed herein. The method includes receiving a screen capture command, determining pixel values of rows of the display device based on the screen parameters, obtaining framebuffer parameters from a framebuffer of the display device, the framebuffer parameters comprising pixel values of rows of the framebuffer, determining whether pixel values of the rows of the framebuffer are substantially equivalent to the pixel values of the rows of the display device, processing screenshot data read from the framebuffer based on the pixel values of the rows of the screen when the pixel values of the rows of the framebuffer are not substantially equivalent to the pixel values of the rows of the screen, and creating a file comprising the screenshot.

Abstract: Computers for supporting multiple virtual reality (VR) display devices and related methods are described herein. An example computer includes a graphics processing unit (GPU) to render frames for a first VR display device and a second VR display device, a memory to store frames rendered by the GPU for the first VR display device and the second VR display device, and a vertical synchronization (VSYNC) scheduler to transmit alternating first and second VSYNC signals to the GPU such that a time period between each of the first or second VSYNC signals and a subsequent one of the first or second VSYNC signals is substantially the same. The GPU is to, based on the first and second VSYNC signals, alternate between rendering a frame for the first VR display device and a frame for the second VR display device.

Abstract: In a graphics processing system, when using a graphics texture that is stored in memory as YUV texture data, the YUV texture data is stored in the texture cache from which it is to be read when generating a render output such that the data values for a chrominance data element and its associated set of one or more luminance data elements of the texture are stored together as a group in the cache. The group of data in the cache is tagged with an identifier for the data values of the chrominance data element and its associated set of one or more luminance data elements that is useable to identify the chrominance data element and its associated set of one or more luminance data elements in the cache, and that is indicative of a position in the YUV graphics texture.