Abstract: A graphics processing unit is configured to process graphics data using a rendering space which is sub-divided into a plurality of tiles. The graphics processing unit comprises one or more processing cores configured to process graphics data. The graphics processing unit also comprises scheduling logic configured to subdivide at least one set of one or more tiles of the rendering space to form a plurality of subunits (e.g. subtiles) and to assign at least some of those subunits to different processing cores for rendering. The subdivision of tiles can be particularly useful for expensive tiles occurring near the end of a render to reduce the impact on the total render time when expensive tiles are scheduled near the end of a render.

Abstract: Techniques that facilitate matrix factorization associated with graphics processing units are provided. In one example, a system includes a first graphics processing unit, a second graphics processing unit and a central processing unit. The first graphics processing unit processes a first data block of a data matrix associated with a matrix factorization system to generate first information for the matrix factorization system. The second graphics processing unit processes a first portion of a second data block of the data matrix separate from a second portion of the second data block to generate second information for the matrix factorization system. The central processing unit processes a machine learning model for the matrix factorization system based on at least the first information provided by the first graphics processing unit and the second information provided by the second graphics processing unit.

Abstract: One embodiment provides for a general-purpose graphics processing device comprising a general-purpose graphics processing compute block to process a workload including graphics or compute operations, a first cache memory, and a coherency module enable the first cache memory to coherently cache data for the workload, the data stored in memory within a virtual address space, wherein the virtual address space shared with a separate general-purpose processor including a second cache memory that is coherent with the first cache memory.

Abstract: Methods, systems, and computer-readable media for capacity reservation for virtualized graphics processing are disclosed. A request is received to attach a virtual GPU to a virtual compute instance. The request comprises one or more constraints. Availability information is retrieved from a data store that indicates virtual GPUs available in a provider network and matching the one or more constraints. A virtual GPU is selected from among the available virtual GPUs in the availability information. The selected virtual GPU is reserved for attachment to the virtual compute instance. The virtual compute instance is implemented using CPU resources and memory resources of a physical compute instance, the virtual GPU is implemented using a physical GPU in the provider network, and the physical GPU is accessible to the physical compute instance over a network.

Abstract: Embodiments described herein provide a graphics processor in which dependency tracking hardware is simplified via the use of compiler provided software scoreboard information. In one embodiment the shader compiler for shader programs is configured to encode software scoreboard information into each instruction. Dependencies can be evaluated by the shader compiler and provided as scoreboard information with each instruction. The hardware can then use the provided information when scheduling instructions. In one embodiment, a software scoreboard synchronization instruction is provided to facilitate software dependency handling within a shader program. Using software to facilitate software dependency handling and synchronization can simplify hardware design, reducing the area consumed by the hardware. In one embodiment, dependencies can be evaluated by the shader compiler instead of the GPU hardware.

Abstract: An apparatus and method for splitting shaders. For example, one embodiment of a method comprises: receiving a request for compilation of a shader in a graphics processing environment; determining whether there is sufficient work associated with the shader to justify splitting the shader into two or more blocks of program code; evaluating the program code of the shader to identify dependencies between the blocks of program code if there is sufficient work; subdividing the shader into the two or more blocks in accordance with the identified dependencies; and individually executing the two or more blocks of code on a graphics processor. In addition, one embodiment includes the operations of determining whether any of the regions that can be subdivided are likely to run faster with different machine configurations than if the shader is executed without being subdivided, and subdividing the shader only for those regions that are likely to run faster with different machine configurations.

Abstract: Systems and methods are provided that may be implemented to electronically link together and cool multiple graphics boards (also known as graphics cards) within an information handling system chassis, such as notebook computer chassis. The multiple graphics boards may be positioned at different levels relative to each other, and may be mounted separate from the main board (e.g., motherboard) in order to achieve a reduced total projective printed circuit board (PCB) area for the combination of the multiple graphics boards and main board. The multiple graphics boards may be stacked on opposite sides of the same thermal cooling module to allow a common thermal cooling module to simultaneously cool a GPU of each of the multiple linked graphics boards, as well as one or more other processors (e.g., central processing units and/or chipsets) mounted to the main board of the system.

Abstract: Disclosed is a data compression method for DeMura table, including steps of: acquiring an original DeMura table of a display panel; designating compensation data in four neighboring rows in the original DeMura table as a fragment to be fetched in a fetch cycle and periodically fetching compensation data per fetch cycle; permuting fetched compensation data so as to create a compressed DeMura table; and storing the compressed DeMura table in a storage device, wherein the step of periodically fetching compensation data includes sub-steps of: fetching the compensation data in odd-numbered columns from the first row of the original DeMura table; and fetching the compensation data in even-numbered columns from the third row and fetching the compensation data in the first column from the third row of the original DeMura table. Also disclosed is a data decompression method for DeMura table. The invention can save storage space and lower cost.

Abstract: An apparatus to facilitate processing of a sparse matrix is disclosed. The apparatus includes a plurality of processing units each comprising one or more processing elements, including logic to read operands, a multiplication unit to multiply two or more operands and a scheduler to identify operands having a zero value and prevent scheduling of the operands having the zero value at the multiplication unit.

Abstract: Devices for coordinating or establishing a direct memory access for a network interface card to a graphics processing unit, and for a network interface card to access a graphics processing unit via a direct memory access are disclosed. For example, a central processing unit may request a graphics processing unit to allocate a memory buffer of the graphics processing unit for a direct memory access by a network interface card and receive from the graphics processing unit a first confirmation of an allocation of the memory buffer. The central processing unit may further transmit to the network interface card a first notification of the allocation of the memory buffer of the graphics processing unit, poll the network interface card to determine when a packet is received by the network interface card, and transmit a second notification to the graphics processing unit that the packet is written to the memory buffer.

Abstract: Systems and method for processing video frames generated for display on a head mounted display (HMD) to a second screen are provided. In one example, a client system having a processor for generating video frames in response to interactive game play of a video game using the HMD is provided. The generated video frames include in-band regions that include the video game content (VGC) to be displayed on the HMD. A processing device having an input interface for receiving the generated video frames. The processing device including extract logic for extracting a portion of the generated video frames, and a codec unit configured to process the portion of the generated video frames. Further included is a graphics processor unit (GPU) for processing the portion of the generated video frames and formatting for display on the second screen. The portion of the generated video frames processed by the GPU being provided to a first output interface of the processing device.

Abstract: An image processor includes a frame buffer configured to collect an image data of pixels and configured to generate frame data, a display controller configured to generate the frame update command based on a vertical synchronizing signal and a frame per second signal representing a number of activating of the frame update signal in a second and an operating part configured to generate the vertical synchronizing signal and the image data. When the frame data is generated, the frame buffer activates a frame update signal in response to a frame update command and outputs the frame data. When the frame per second signal is less than a predetermined threshold voltage, the operating part sets a lower limit of a range of a frequency to a predetermined minimum frequency.

Abstract: An apparatus to facilitate thread scheduling is disclosed. The apparatus includes logic to store barrier usage data based on a magnitude of barrier messages in an application kernel and a scheduler to schedule execution of threads across a plurality of multiprocessors based on the barrier usage data.

Abstract: A method tracks a pose of an object in a field of view of a camera; derives movement of the display apparatus or movement in the field of view using at least one of: the sensor data and the image data; determines, using the processor, whether or not the derived movement exceeds a first threshold; if the derived movement exceeds the first threshold, continues tracking the pose of the object; and if the movement does not exceed the first threshold: (1) stops tracking the pose of the object and (2) displays, using the display, the image based on a previously derived pose of the object.

Abstract: An apparatus for providing an external power supply, memory device, camera, and/or other peripheral capabilities to a head-mounted data collection device may include a first portion releasably connecting to the data collection device. The first portion may have a first data port interface configured for connection to a corresponding data port interface of the data collection device. The apparatus may have a second portion releasably connectable to the first portion, the second portion including an internal data port interface configured for connection to a corresponding internal data port interface of the first portion, a power cell module, and a power supply interface configured for connection to a corresponding power supply input of the head-mounted wearable data collection device. The first portion and/or the second portion may include interface logic for receiving data via the first data port and command logic for issuing commands to the data collection device.

Abstract: In a display controller, output surface data from a composition processing stage 22 is received by and stored in a local latency hiding buffer 40 of a memory write subsystem 31 before being written out to an external memory. The local buffer 40 of the memory write subsystem 31 signals when it is “full”, and in response thereto the inputting of output surface data to the local buffer 40 is stopped until the current line of the output surface has been finished, and then started again when the next line of the output surface begins. The writing of any data for the line of the output surface that was being written to the local buffer 40 that is already present in the local buffer 40 and not yet written to the external memory is also skipped, and it is recorded that the output surface line in question is not properly stored in the external memory.

Abstract: A display method and display device are provided. The method includes: detecting whether a displayed content in a display screen changes; in response to detecting that the displayed content does not change, controlling the display screen to update alternately display data respectively corresponding to odd pixels and even pixels in each row of display unit. The number of updated pixels of the display screen each time may be reduced, while the original refresh frequency is maintained, so the problem that the splash screen phenomena is caused in the display screen by reducing the refresh frequency of the display screen may be solved, thus achieving effects of avoiding the splash screen phenomena of the display screen and of reducing the power consumption of the display screen while maintaining the original refresh frequency of the display screen.

Abstract: Systems, methods, and computer readable media to encode and execute an indirect command buffer are described. A processor creates an indirect command buffer that is configured to be encoded into by a graphics processor at a later point in time. The processor encodes, within a command buffer, a produce command that references the indirect command buffer, where the produce command triggers execution on the graphics processor a first operation that encodes a set of commands within the data structure. The processor also encodes, within the command buffer, a consume command that triggers execution on the graphics processor a second operation that executes the set of commands encoded within the data structure. After encoding the command buffer, a processor commits the command buffer for execution on the graphics processor.

Abstract: Techniques are disclosed relating to storage techniques for storing primitive information with vertex re-use. In some embodiments, graphics circuitry aggregates primitive information (including vertex data) for multiple primitives into a primitive block data structure. This may include storing only a single instance of a vertex for multiple primitives that share the vertex. The graphics circuitry may switch between primitive blocks, with one being active and the others non-active. For non-active primitive blocks, the graphics circuitry may track whether vertex identifiers have been used for a new vertex, which may prevent vertex re-use. If an identifier is not used for a new vertex, however, a vertex may be re-used across deactivation and reactivation of a primitive block.

Abstract: One embodiment provides for a graphics processor comprising a translation lookaside buffer (TLB) to cache a first page table entry for a virtual to physical address mapping for use by the graphics processor, the first page table entry to indicate that a first virtual page is cleared to a clear color and a graphics pipeline module to bypass a memory access for the first virtual page based on the first page table entry.