Patents Examined by Joni Y. Chang
  • Patent number: 6113701
    Abstract: An improved semiconductor device manufacturing system and method is shown. In the system, undesirable sputtering effect can be averted by virtue of a combination of an ECR system and a CVD system. Prior to the deposition according to the above combination, a sub-layer can be pre-formed on a substrate in a reaction chamber and transported to another chamber in which deposition is made according to the combination without making contact with air, so that a junction thus formed has good characteristics.
    Type: Grant
    Filed: March 31, 1994
    Date of Patent: September 5, 2000
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Shunpei Yamazaki
  • Patent number: 6040212
    Abstract: Methods of forming trench-gate semiconductor devices using sidewall implantation techniques include the steps of forming a semiconductor substrate containing a trench-gate semiconductor device therein (e.g., MOSFET, IGBT) and then implanting dopants of predetermined conductivity type into a sidewall of the trench to adjust the threshold voltage of the semiconductor device. In particular, a method is provided which comprises the steps of forming a semiconductor substrate containing a trench therein at a first face thereof, a body region of second conductivity type (e.g., P-type) extending adjacent a sidewall of the trench and a source region of first conductivity type in the body region and extending adjacent a sidewall of the trench and adjacent the first face. An electrically insulating region (e.g., SiO.sub.2) is also formed on a sidewall of the trench and an electrically conductive region is formed in the trench.
    Type: Grant
    Filed: April 4, 1997
    Date of Patent: March 21, 2000
    Assignee: Fairchild Korea Semiconductor, Ltd.
    Inventor: Hyun-Chul Kim
  • Patent number: 5919310
    Abstract: A continuous film-forming apparatus includes a plurality of reaction chambers each capable of forming a semiconductor film with a different chemical composition. The reaction chambers are arranged such that a substrate web on which a film is to be formed can be hermetically moved through each of the reaction chambers under a vacuum condition. A gas gate is disposed at a central position between each pair of adjacent reaction chambers, with each gas gate provided with a slit for communication between the adjacent reaction chambers.
    Type: Grant
    Filed: February 29, 1996
    Date of Patent: July 6, 1999
    Assignee: Canon Kabushiki Kaisha
    Inventors: Yasushi Fujioka, Shotaro Okabe, Masahiro Kanai, Takehito Yoshino, Akira Sakai, Tadashi Hori
  • Patent number: 5918120
    Abstract: A method and structure are described for making DRAM devices having bit line contacts for memory cells and landing plugs for peripheral devices with a Ti/TiN barrier layer patterned to form bit lines and local interconnections. FETs are formed on the substrate for memory cells and for devices in the peripheral area. A planar first insulating layer is deposited, and contact openings are formed to the devices. A Ti/TiN barrier layer is deposited in the contact openings and a tungsten (W) layer is deposited and selectively etched back to the barrier layer. The barrier layer is then patterned to form bit lines and local interconnections. A second insulating layer is deposited, and capacitor node contact openings are etched and filled with polysilicon to form node contacts on which capacitors are fabricated. A planar third insulating layer is formed and multilevel contact openings are etched to landing plugs.
    Type: Grant
    Filed: July 24, 1998
    Date of Patent: June 29, 1999
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Jenn Ming Huang
  • Patent number: 5899716
    Abstract: A method of creating an STC structure, used for high density, DRAM designs, has been developed. The process consists of creating a storage node electrode, for the STC structure, with increased surface area, resulting from the formation of protruding polysilicon shapes. The protruding polysilicon shapes are obtained using dielectric regions as a mask during a selective, anisotropic RIE procedure, used to define the storage node electrode shape. The dielectric regions are created via oxygen ion implantation into exposed regions of a polysilicon layer. An anneal is used to convert the oxygen implanted polysilicon regions, to dielectric regions.
    Type: Grant
    Filed: May 19, 1997
    Date of Patent: May 4, 1999
    Assignee: Vanguard International Semiconductor Corporation
    Inventor: Horng-Huei Tseng
  • Patent number: 5888863
    Abstract: A method is described for forming a dynamic random access memory cell with an increased capacitance capacitor. Semiconductor devices including a capacitor node contact region are formed. A layer of silicon nitride and an insulating layer are deposited over the devices. A contact is opened through the insulating and silicon nitride layers to the capacitor node contact region. A first layer of polysilicon is deposited over the insulating layer and within the contact opening. A layer of silicon oxide is deposited over the first polysilicon layer. The silicon oxide layer is patterned so as to leave this layer only in the area of the planned capacitor and extending outward from the contact opening a first distance. The first polysilicon layer is patterned so as to leave this layer only in the area of the planned capacitor and extending outward from the contact opening a second distance smaller than the first distance. A second layer of polysilicon is deposited over the silicon oxide layer.
    Type: Grant
    Filed: May 16, 1996
    Date of Patent: March 30, 1999
    Assignee: Vanguard International Semiconductor Corporation
    Inventor: Horng-Huei Tseng
  • Patent number: 5866457
    Abstract: A new semiconductor structure for a ROM device and a method for fabricating the same are provided. The ROM device includes a plurality of trench-type source/drain regions which serve as a plurality of bit lines for the ROM device. By this method, the conventional step of using ion implantation to form the bit lines can be eliminated. Further, an insulating layer is formed between the source/drain regions and the underlying substrate such that the leakage current in the junction between the source/drain regions and the substrate can be minimized. The ON/OFF state of each of the MOSFET memory cells of the ROM device is dependent on whether the associated channel region comes into lateral contact with the neighboring source/drain regions through a mask removed portion of the insulating layer.
    Type: Grant
    Filed: April 15, 1997
    Date of Patent: February 2, 1999
    Assignee: United Microelectronics Corp.
    Inventor: Jemmy Wen
  • Patent number: 5858837
    Abstract: A method of manufacturing a semiconductor memory device, comprising the steps of: forming a gate electrode with an insulating spacer, forming a first silicon oxide film by high-temperature chemical vapor deposition (CVD), forming n-type source/drain regions, forming a first insulating interlayer and forming a bit line; forming a second silicon oxide film by low-temperature CVD, forming a BPSG film, and annealing the second silicon oxide film and the BPSG film by first annealing to form a second insulating interlayer constituted by the stacked films; forming a third silicon oxide film by low-temperature CVD, and annealing the third silicon oxide film by second annealing; forming a node contact hole through the annealed third silicon oxide film, the second insulating interlayer, the first insulating interlayer, and the first silicon oxide film; forming an amorphous silicon film doped n-type at the time of the film formation, patterning the amorphous silicon film to form an amorphous silicon film pattern, and re
    Type: Grant
    Filed: November 10, 1997
    Date of Patent: January 12, 1999
    Assignee: NEC Corporation
    Inventors: Takashi Sakoh, Ichiro Honma
  • Patent number: 5849618
    Abstract: A method for fabricating a capacitor for a semiconductor device includes the steps of depositing an insulating layer on a substrate, selectively removing the insulating layer and forming a contact hole, forming a first electrode in the contact hole, removing the insulating layer to expose a portion of the first electrode, and sequentially forming a dielectric layer and a second electrode on the exposed portion of the first electrode.
    Type: Grant
    Filed: May 21, 1996
    Date of Patent: December 15, 1998
    Assignee: LG Semicon Co., Ltd.
    Inventor: Yoo-Chan Jeon
  • Patent number: 5843822
    Abstract: A method of fabricating double-side corrugated cylindrical capacitor of high density Dynamic Random Access Memory (DRAM) cells. The corrugated capacitor shape is achieved by depositing the thermal chemical vapor deposition (CVD) oxide and the plasma-enhanced CVD (PECVD) oxide alternating layers. Then, the thermal CVD oxide and the PECVD oxide layers are vertically etched to form two trenches followed by laterally etched by hydrofluoric acid (HF). Because hydrofluoric acid (HF) etches the thermal CVD oxide at a slower rate than etches the PECVD oxide, a cavity is formed in each PECVD oxide layer along the trenches. Finally, polysilicon layer is deposited filling into the trenches. Therefore, the double-side corrugated shape capacitor surface is created that increases the surface area of the capacitor considerably.
    Type: Grant
    Filed: February 5, 1997
    Date of Patent: December 1, 1998
    Assignee: Mosel Vitelic Inc.
    Inventors: Liang-Choo Hsia, Thomas Chang
  • Patent number: 5840606
    Abstract: A method for manufacturing a comb-shaped lower electrode for a DRAM capacitor including the steps of providing a substrate having a transistor and an insulating layer formed thereon, wherein the insulating layer contains a contact window opening exposing a source/drain region of the transistor; then, forming a polysilicon layer over the insulating layer, the contact window opening and the exposed source/drain region; next, forming a hemispherical grain silicon over the polysilicon layer. Thereafter, an oxide layer is formed over the hemispherical grain silicon, and then a silicon nitride layer is formed over the gaps between the hemispherical grain silicon exposing portions of the oxide layer. In the subsequent step, a plurality of hard mask layers are formed over the oxide layer not covered by the silicon nitride layer, and finally the silicon nitride layer, the oxide layer and portions of the polysilicon layer are removed using the hard mask layers to form a plurality of trenches.
    Type: Grant
    Filed: November 25, 1997
    Date of Patent: November 24, 1998
    Assignee: United Semiconductor Corp.
    Inventor: Claymens Lee
  • Patent number: 5840591
    Abstract: A buried bit line DRAM cell and a manufacturing method thereof are provided. The buried bit line DRAM cell has a buried bit line formed into a trench which isolates devices, the buried bit line being isolated from a semiconductor substrate, a gate formed to be orthogonal to the bit line on the substrate, a first insulating layer formed to insulate the gate, a source and a drain of a transistor formed on the substrate at both sides of the gate, a self-aligned bit line contact formed between the first insulating layers for making contact between the drain and the buried bit line, and a self-aligned buried contact formed between the first insulating layers for making contact between the source and a storage electrode. According to the above structure, misalignment between the gate and the bit line and the excessive exposure to thermal processing which are inherent in conventional Buried Bit Line cells can be avoided and the design rule margin can be improved.
    Type: Grant
    Filed: November 30, 1995
    Date of Patent: November 24, 1998
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jae-Kwan Park, Jong-Woo Park
  • Patent number: 5824563
    Abstract: A method for forming the lower electrode of a capacitor used for fabricating a 1-Gbit or above DRAM, using a material having a high dielectric constant, is used in a method for manufacturing a storage capacitor of a VLSI semiconductor device. The lower electrode, which is to be in contact with a high dielectric film, is formed to have a triple-structured storage node pattern. The lowest layer of the lower electrode is formed with TiN which serves as a barrier against the diffusion of impurities from a lower substrate. The middle layer of the lower electrode is formed with RuO.sub.2 which is easy to pattern. The uppermost layer of the lower electrode is formed with Pt which has excellent leakage current properties.
    Type: Grant
    Filed: November 17, 1995
    Date of Patent: October 20, 1998
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Cheol-sung Hwang
  • Patent number: 5824582
    Abstract: A method is disclosed for a manufacturing process of forming a high capacitance capacitor in a DRAM cell. A semiconductor substrate having a switching MOS transistor comprising a word line and a bit line is provided. A first dielectric is deposited over the substrate and planarized. Contact hole is etched in the first dielectric until the substrate is exposed. A doped first polysilicon is blanket deposited over the substrate filling the holes. A trench is next formed partially in the first polysilicon layer over the contact hole but not reaching the hole. A second dielectric material is deposited over the substrate filling the trench. The dielectric layer is then plasma etched back so as to form a dielectric plug in the trench. Using now the dielectric plug as a mask, the first polysilicon layer is then removed to a predetermined thickness by means of reactive ion etch. A second polysilicon is next formed conformally over the first polysilicon layer covering the dielectric plug.
    Type: Grant
    Filed: June 4, 1997
    Date of Patent: October 20, 1998
    Assignee: Vanguard International Semiconductor Corporation
    Inventor: Horng-Huei Tseng
  • Patent number: 5817532
    Abstract: There are disclosed a ferroelectric thin film device and a method for making the same. The ferroelectric thin film device includes a bottom electrode formed on a substrate, a ferroelectric thin film formed on the bottom electrode to contain a predetermined amount of Ta and have grains arranged in a regularly repeating pattern, and a top electrode formed on the ferroelectric thin film. The method for making a ferroelectric thin film includes the steps of forming a bottom electrode on a substrate, forming on the bottom electrode a Ta doped ferroelectric thin film, forming a top electrode on the ferroelectric thin film at regular intervals, and performing a rapid thermal annealing process on the ferroelectric thin film, using a radiant heating device, to induce crystallization.
    Type: Grant
    Filed: April 29, 1996
    Date of Patent: October 6, 1998
    Assignee: Seungki Joo
    Inventors: Seungki Joo, Jaehyun Joo
  • Patent number: 5804500
    Abstract: An antifuse comprises a lower electrode formed from a metal layer in a microcircuit. A interlayer dielectric layer is disposed over the lower electrode and has an aperture formed therein. A conductive plug, formed from a material such as tungsten, is formed in the aperture. The upper surface of the interlayer dielectric is etched back to create a raised portion of the plug. The upper edges of the plug are rounded. An antifuse layer, preferably comprising a silicon nitride, amorphous silicon, silicon nitride sandwich incorporating a thin silicon dioxide layer above or below the amorphous silicon layer or such a sandwich structure covered by a titanium nitride layer, is disposed above the plug. An upper electrode, preferably comprising a metal layer is disposed over the antifuse layer.
    Type: Grant
    Filed: June 4, 1996
    Date of Patent: September 8, 1998
    Assignee: Actel Corporation
    Inventors: Frank W. Hawley, John L. McCollum, Ying Go, Abdelshafy Eltoukhy
  • Patent number: 5804478
    Abstract: A type of semiconductor device with a configuration characterized by the fact that an electroconductive film (90) is formed beforehand in connection to step (54a) of insulating film(54), and an electroconductive layer (63) with step from the aforementioned electroconductive film is coated to form the side contact of the memory cell. Even in the case when breakage takes place in electroconductive layer (63), the electrical conduction is still maintained via electroconductive film (90), and no wire breakage, in effect, takes place. In addition, it is possible to form the pattern for the aforementioned electroconductive layer by, for instance, etching back method without applying a special mask; hence, the manufacturing process is simplified.
    Type: Grant
    Filed: August 15, 1996
    Date of Patent: September 8, 1998
    Assignee: Texas Instruments Incorporated
    Inventors: Toshiyuki Nagata, Hiroyuki Yoshida, Takayuki Niuya, Yoshihiro Ogata
  • Patent number: 5803974
    Abstract: A process for forming a deposited film on a substrate according to the chemical vapor deposition method comprises previously forming excited species of a gas phase compound containing atoms which become constituents constituting said deposited film, supplying the excited species onto the surface of said substrate and effecting photoirradiation on said substrate surface, thereby forming the deposited film through the surface reaction.
    Type: Grant
    Filed: June 7, 1995
    Date of Patent: September 8, 1998
    Assignee: Canon Kabushiki Kaisha
    Inventors: Nobuo Mikoshiba, Tadahiro Ohmi, Kazuo Tsubouchi, Kazuya Masu, Nobumasa Suzuki
  • Patent number: 5800619
    Abstract: A substantially planar coil of a vacuum plasma processor has plural turns for exciting gas in the processor to a plasma state in response to r.f. coil energization. The coil is located outside the processor and surrounded by a shield tending to cause magnetic flux coupled from peripheral portions of the coil to the gas to be less than magnetic flux coupled from interior portions of the coil to the gas. The coil is arranged so magnetic flux derived from a center portion of an area circumscribed by the coil is less than the magnetic flux derived from all other areas circumscribed by the coil. The magnetic flux is such that the density of the plasma in the processor on a processed substrate is relatively uniform even though the coil exhibits transmission line properties so there are substantial peak-to-peak current variations along the length of the coil.
    Type: Grant
    Filed: June 10, 1996
    Date of Patent: September 1, 1998
    Assignee: Lam Research Corporation
    Inventors: John Patrick Holland, Michael S. Barnes
  • Patent number: 5798289
    Abstract: A method of manufacturing a semiconductor memory device having stacked capacitors is disclosed. After forming a capacitor isolating layer on an insulation layer and forming a contact hole in the insulation layer, a first conductive layer is formed on the insulating layer and the capacitor isolating layer and on an inner surface of the contact hole. The first conductive layer is partially etched and removed by using an etch-back technique to be isolated into a first capacitor portion and a second capacitor portion. A dielectric layer is formed on the first conductive layer. A second conductive layer is formed on the dielectric layer.
    Type: Grant
    Filed: September 10, 1996
    Date of Patent: August 25, 1998
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Natsuo Ajika, Hideaki Arima, Atsushi Hachisuka