Abstract: A polysilicon film having a rough surface is formed by a reduced pressure CVD method at a temperature of 575.degree. C. and a deposition pressure of 0.2 Torr. Silicon ions are implanted into the polysilicon film having a rough surface. Thus, the tips of concaves and convexes at the rough surface of the polysilicon film are rounded. Then, this polysilicon film having a rough surface is patterned to form a storage node. A cell plate is formed to cover the storage node with a capacitor insulating layer therebetween. Consequently, a semiconductor device capable of suppressing leak current between capacitor electrodes can be manufactured.

Abstract: A process for fabricating MOSFET devices, for a SRAM cell, using a polycide contact structure, self-aligned to an underlying source and drain region, has been developed. This process features the use of a high temperature, rapid thermal anneal step, used to dissolve native oxide at the polycide-source and drain interface, thus reducing the resistance at the interface of the polycide self-aligned structure, and the underlying source and drain area.

Abstract: A unique DRAM structure has increased capacitance by using a parallel fin capacitor structure. A preferred embodiment of the invention includes a silicon substrate having a first conductivity type. Field oxide (FOX) regions are defined in the substrate to separate DRAM cells. Drain and source regions are formed in the substrate by forming in the substrate regions. On the substrate surface and between the drain and source, a gate region is formed. The gate region comprises a gate oxide, a first polysilicon layer (Poly-1) doped to have a second conductivity type opposite the first conductivity type, a tungsten silicide (WSi) layer, and an oxide layer, such as SiO.sub.2 or SiN. Oxide or TEOS (tetraethylorthosilicate) spacers cover the sides of the gate region. Above the gate region is an insulating layer of TEOS. A second polysilicon layer (Poly-2) having the second conductivity type contacts the source region and forms a bitline. Layers of WSi, oxide or thin TEOS, and Si.sub.y N.sub.x, such as Si.sub.3 N.sub.

Abstract: A method for fabricating chalcogenide memories in which ultra-small pores are formed in insulative layers using disposable spacers. The chalcogenide memory elements are positioned within the ultra-small pores. The chalcogenide memory elements thus defined have minimum lateral dimensions ranging from approximately 500 to 4000 Angstroms.

Abstract: A method of fabricating a capacitor of a semiconductor memory device includes the steps of: forming an interlevel insulating layer on a semiconductor substrate on which the capacitor will be formed, selectively etching a portion of the interlevel insulating layer placed on a capacitor forming portion to form a capacitor node hole, and forming a first temporary layer on the interlevel insulating layer, including a portion of the interlevel insulating layer in which the capacitor node hole is formed; forming a contact hole beneath the capacitor node hole in a capacitor contact portion; forming a conductive layer on the first temporary layer to bury the contact hole and the capacitor node hole, and then forming a second temporary layer on the conductive layer; etching back the second temporary layer through anisotropic etching process to expose the conductive layer, and to simultaneously form a temporary pillar layer inside the capacitor node hole, the temporary pillar layer being substantially surrounded by the

Abstract: A plasma guard member that has the configuration of a flat concentric ring is used in a vacuum process chamber equipped with a plasma reaction chamber, a plasma source and a lower chamber which houses an electrostatic chuck for preventing charged particles from drifting or diffusing to the lower chamber and contact the electrostatic chuck such that the substrate holding capability of the chuck is not adversely affected.

Abstract: A planar coil exciting a plasma of an r.f. vacuum plasma processor for a workpiece processed surface in a chamber includes plural turns. The coil, chamber and workpiece are arranged to produce in the chamber a magnetic flux having substantially greater density in peripheral portions of the coil and chamber than in a center portion of the chamber and coil so a substantially uniform plasma flux is incident on a processed surface of the workpiece.

Abstract: A method of fabricating a rugged-crown shaped capacitor on a semiconductor substrate is provided. Specifically, the method can be applied for fabricating a storage capacitor of a DRAM cell. A doped polysilicon layer is deposited on the substrate and patterned to retain the portion of the doped polysilicon layer within a planned region of the capacitor. Next, an undoped polysilicon layer is deposited on the doped polysilicon layer and the substrate and etched back as undoped polysilicon spacers. Then the doped layer and the undoped spacers are selectively etched by a hot H.sub.3 PO.sub.4 solution to form a crown-shaped node of the capacitor with a rugged surface. Then the undoped portion of the crown-shaped node of the capacitor is doped and the rugged-crown shaped node forms a conductive plate of the DRAM capacitor, providing a rugged-crown shaped capacitor having a larger area to increase its capacitance.

Abstract: Two embodiments of a method are described for fabricating a DRAM cell having a T or Y shaped capacitor connected to a MOS transistor with source and drain regions. In a first embodiment, the method comprises using two masks to form a cylindrical hole partial through the insulating layer and a concentric contact hole over the source. A first conductive layer is formed over the first insulating layer, at least completely filling the trench and filling the contact hole. In a key step, the first polysilicon layer is chemically mechanically polished thereby forming a T shaped storage electrode. Next, a capacitor dielectric layer and a top electrode are sequentially formed over at least the T shaped storage electrode. The second embodiment form the contact hole and trench as described above. A conformal first conductive layer is formed over the first insulating layer, filling the contact hole and covering the sidewalls and bottom of the trench, but not filling the trench.

Abstract: An inductively coupled RF plasma reactor for processing semiconductor wafer includes a reactor chamber having a side wall and a ceiling, a wafer pedestal for supporting the wafer in the chamber, an RF power source, apparatus for introducing a processing gas into the reactor chamber, and a coil inductor adjacent the reactor chamber connected to the RF power source, the coil inductor including (a) a side section facing a portion of the side wall and including a bottom winding and a top winding, the top winding being at a height corresponding at least approximately to a top height of the ceiling, and (b) a top section extending radially inwardly from the top winding of the side section so as to overlie at least a substantial portion of the ceiling.

Abstract: A first interlayer insulating film having a second contact hole is formed on a main surface of a semiconductor substrate 1 in a peripheral circuitry. A second plug electrode of the same material as a first plug electrode in a memory cell array is formed in the second contact hole. A pad layer is formed over the second plug electrode and a top surface of the first interlayer insulating film. The pad layer and a capacitor lower electrode are made of the same material. The pad layer is covered with the second interlayer insulating film. A third contact hole is formed at a portion of the second interlayer insulating film located above the pad layer. A first aluminum interconnection layer is formed in the third contact hole. Thereby, a contact can be formed easily between the interconnection layer and the main surface of the semiconductor substrate in the peripheral circuitry of a DRAM, and a manufacturing process can be simplified.

Abstract: A method for fabricating a storage electrode is designed to avoid the problems of polysilicon bridge and undercut. First, a substrate having a transistor is provided. An insulating layer is then deposited over the substrate. A contact hole is then formed in the insulating layer down to the source/drain region of the transistor. A thin polysilicon layer is then deposited and further patterned at least at the periphery of the contact hole and on the upper surface of the source/drain region. Finally, an anisotropical epitaxial polysilicon layer is formed on the upper surface of the first polysilicon layer.

Abstract: A method of manufacturing process of a semiconductor device, including the steps of forming a plurality of first trenches in a checkered configuration in a substrate, each of the first trenches having an opening; introducing a first conductivity type impurity from a surface of the substrate so as to form a first conductivity type well in a upper portion of the substrate; forming a capacitor insulating film on a surface of each of the first trenches and burying a storage electrode in each of the first trenches so as to form a trench capacitor in each of the first trenches; burying a first silicon film on each of the storage electrodes of the trench capacitors in the first trenches, etching back each of portions of the first silicon film and removing each of portions of the capacitor insulating films so as to expose portions of side surfaces of the first conductivity type well facing the first trenches; burying a second silicon film doped with a second conductivity type impurity in each of concave portions surr

Abstract: A retractable probe system (12) senses in situ a plurality of predetermined process parameters of a wafer (24) fabrication environment (16) and includes a sensing device (47) for sensing the predetermined process parameters, a probe arm (46) for holding sensing device (47) and having sufficient length to extend sensing device (47) into a predetermined location of the fabrication environment (16). A housing (36) receives the sensing device (47) and probe arm (46). A locator mechanism (52, 42, and 44) controllably locates sensing device 47) and probe arm (46) within fabrication environment (16) and within housing (36). An isolator mechanism (34) isolates sensing device (47) and probe arm (46) within housing (36) and essentially out of gases communication with fabrication environment (16). Cleaning mechanism (54) cleanses sensing device (47) within housing (36) and permits sensing device (47) to be immediately thereafter located in fabrication environment (16).

Abstract: A multi-region material structure and process for forming capacitors and interconnect lines for use with integrated circuits provides (1) capacitor first or bottom electrodes comprising a transition-metal nitride; (2) a capacitor dielectric comprising a transition-metal oxide; (3) capacitor second or top electrodes comprising a transition-metal nitride, a metal or multiple conductive layers; (4) one or more levels of interconnect lines; (5) electrical insulation between adjacent regions as required by the application; and (6) bonding between two regions when such bonding is required to achieve strong region-to-region adhesion or to achieve a region-to-region interface that has a low density of electrical defects.

Abstract: The present invention relates to relates to a hydrogenated amorphous silicon carbide used as the surface protecting layer of the photosensitive member for electrohotographic apparatus. In view of not allowing generation of blurring of photosensitive member under the high humidity atmosphere, the content (x) of carbon in the hydrogenated amorphous silicon carbide expressed by the general formula a-Si.sub.1-x C.sub.x :H is in the range of 0.4.ltoreq.x.ltoreq.0.8 and a ratio (TO/TA) of the peak (TO) amplitude appearing in the vicinity of 480 cm.sup.-1 and the peak (TA) amplitude appearing in the vicinity of 150 cm.sup.-1 observed by the laser Raman spectroscopy measurement using the excitation laser of Ar.sup.+ 488 nm is set to 2.0 or higher.

Abstract: A capacitor structure of a semiconductor device which includes a semiconductor substrate, a first metal layer formed on the substrate, and a second metal layer formed on the first metal layer. The first metal layer has a nitridation-treated film along its outer surface. A tungsten film having a rugged surface is formed on the entire outer surfaces of the first and second metal layers. Because of the nitridation-treated film along the first layer, the tungsten film will be uniformly distributed along the first and second metals. A thin dielectric film is then formed on the surface of the tungsten, followed by a third metal layer formed on the dielectric film.

Abstract: A semiconductor processing method of making electrical contact to a node received within a mass of insulating dielectric material includes, a) providing a node within a mass of insulating dielectric material; b) first stage etching into the insulating dielectric material over the node in a manner substantially selective relative to the node; c) after the first stage etching, second stage etching the dielectric material in a manner which increases a degree of sidewall polymerization over that occurring in the first stage etching and in a manner substantially selective relative to the node; and d) after the second stage etching, third stage etching the dielectric material with a degree of sidewall polymerization which is less than that of the second stage etching and in a manner substantially selective relative to the first node. An alternate method provides an etch stop annulus cap overlying an electrically conductive ring which projects from a primary insulating layer.

Abstract: A method for fabricating a semiconductor device having a capacitor exhibiting improved insulating and ferroelectric characteristics. The method involves forming a lower insulating layer over a semiconductor substrate, selectively removing the lower insulating layer to form a contact hole, forming a ruthenium film over the lower insulating layer, selectively removing the ruthenium film, thereby forming a lower electrode, and forming a ruthenium oxide film over the lower electrode. A method for forming a metal wiring is also provided.

Abstract: Mounted on a single semiconductor substrate are a DRAM, MOS transistor, resistor, and capacitor. The gate electrode of the DRAM and the gate electrode of the MOS transistor are formed by a common layer (i.e., a first-level poly-Si layer). The storage electrode of the DRAM. the resistor, and the lower electrode of the capacitor are formed by a common layer (i.e., a third-level poly-Si layer). The plate electrode of the DRAM and the upper electrode of the capacitor are formed by a common layer (i.e., a fourth-level poly-Si layer).