Abstract: A plasma reactor has a reactor chamber for containing a semiconductor wafer to be processed and gas inlet apparatus for introducing an ionizable gas into the chamber, a variable frequency RF power source, an RF antenna near the chamber, the antenna connected to the RF power source for coupling RF power to the ionizable gas to produce a plasma therefrom, a power sensor connected to the antenna for sensing either (or both) transmitted power to the plasma or reflected power to said source, and a control circuit connected to a control input of the variable frequency RF power source and responsive to the power sensor for changing the frequency of the variable frequency RF power source so as to either increase the transmitted power or decrease the reflected power, so as to provide an accurate RF match instantly responsive to changes in plasma impedance.

Abstract: In accordance with still another aspect of this invention, a set of cross-coupled inverters provide a bistable flip flop formed on a semiconductor substrate with a pair of FOX regions defining an area on the surface of a substrate. The substrate is composed of a semiconductor material with a pair of buried contact regions in the silicon substrate juxtaposed with the FOX regions. A control gate electrode is formed on a gate oxide layer on the surface of the substrate between the pair of the FOX regions. A source region and drain region are formed in the substrate juxtaposed with the control gate electrode to form a parasitic FET device between the FOX regions, the source region and the drain region and reaching to separate ones of the buried contact regions. An interpolysilicon dielectric layer over the control gate electrode covers the device and the power supply conductor passes over the control gate electrode.

Abstract: In one aspect, the invention is embodied in a plasma reactor for processing a semiconductor wafer, the reactor having a pedestal focus ring surrounding the periphery of the wafer for reducing the process etch rate near the wafer periphery, and plural openings through the pedestal focus ring which permit passage therethrough of particulate contamination, thereby reducing accumulation of particulate contamination near the wafer periphery. In another aspect, in order to reduce corrosive wear of the chamber walls, a removable gas distribution focus ring shields the side walls of the plasma reactor from reactive gases associated with processing of the semiconductor wafer.

Abstract: A plasma reactor for processing a semiconductor wafer inside a vacuum chamber has an array of gas distribution orifices in said chamber facing respective underlying portions of a top surface of said wafer, a gas flow supply, apparatus for individually coupling gas to respective ones of said gas distribution orifices from said gas flow supply at respective individual gas flow rates whereby respective gas flow rates over said respective underlying portions of said top surface of said wafer are respectively determined and apparatus for igniting a plasma inside said chamber from gases contained therein for processing said wafer.

Abstract: In an inductively coupled RF plasma reactor having an inductive coil antenna connected through an RF impedance match network to an RF power source, capacitive coupling from the antenna to the plasma is reduced by isolating the coil antenna from the RF power source by an isolation transformer, so that the potential of the coil antenna is floating. The output of the RF impedance match network is connected across the primary winding of the isolation transformer while the floating coil antenna is connected across the secondary winding of the isolation transformer.

Abstract: An inductive coupling plasma processing apparatus is equipped with a dielectric portion through which high-frequency electric power is introduced and in which a plasma discharge is generated, and the antenna for supplying a discharge chamber with electric power is arranged near the dielectric portion. The dielectric portion is formed on a vacuum chamber having an inside space with low pressure, into which a reactive gas is introduced. The antenna surrounds the dielectric portion and the area of a nearest surface facing the dielectric portion is minimized. The antenna is desired to be so configured that a shape of its cross section perpendicular to a flow direction of a high-frequency current is a flat rectangle, and a long side of the cross section is substantially perpendicular to an outside surface of the dielectric portion.

Abstract: A photo-excited processing apparatus includes a reaction chamber to be filled with reaction gas, photo-excitation means for irradiating a light beam from light source means through a light transmissive window formed in the reaction chamber to excite the raw gas, and multi-holed transparent diffusion means arranged between the light transmissive window of the reaction chamber and a substrate to be mounted in the reaction chamber. The multi-holed transparent diffusion means has a diffusion plane on at least one surface thereof having a plurality of holes formed therein and being transparent to the light beam.

Abstract: A read only memory semiconductor integrated circuit device includes an improved cell region and a method of manufacture therefor. The improved cell region includes a recessed dielectric region overlying a gate electrode region. Such recessed dielectric region allows for an implanting or coding step to occur after the dielectric layer is applied to the surface of the device. Coding of the ROM device during a latter processing step shortens product turn-around-time. The improved cell also includes an improved method of manufacture. Such method provides for a dielectric layer formed over a gate electrode of a partially completed device. The method further provides etching the upper portion of the dielectric layer overlying the gate electrode to form a recessed region. A step of coding or implanting is then performed to change the device from enhancement mode into depletion mode, thereby providing the ROM code for the designated cell.

Abstract: A gate wire is formed so as to extend from an active area to a separation, and an impurity diffused area is formed on each side of the gate electrode located on the active area. A contact member for connecting the gate wire to a first layer aluminum interconnection formed in an upper layer of the gate wire is in contact with the gate wire at a portion located on the active area. The utilization ratio of the active area is thus improved, and hence, the width of the separation can be minimized. In addition, by eliminating a mask alignment margin from the gate wire and suppressing the width of the gate wire not to exceed the width of the contact member, the occupied area of a semiconductor apparatus can be reduced.

Abstract: A method of manufacturing a capacitor for use in a DRAM. The method includes forming an isolation layer over a substrate, forming a nitride layer over the isolation layer, forming a hole in the isolation and nitride layers, forming a polysilicon plug in the hole, growing an oxide plug from an upper portion of the polysilicon plug, removing the nitride layer, forming a polysilicon spacer around the oxide plug, and removing the silicon dioxide plug. Additional steps include depositing a dielectric layer onto the polysilicon sidewall and plug, and depositing a third polysilicon layer onto the dielectric layer.

Abstract: An improved method for forming a dynamic random access memory (DRAM) capacitor with increased capacitance is disclosed. The method includes forming an oxide layer on a semiconductor substrate with a metal-oxide-semiconductor field effect transistor (MOSFET) conventionally formed therein and thereon. A planarized silicon nitride layer is then formed on the oxide layer. Then alternating layers of dielectric layers having different etch rates are formed on the silicon nitride layer. Standard photolithographic methods are used to etch a trench through the dielectric layers and the silicon nitride layer to expose the source region of the MOSFET. The trench is then isotropically etched, forming rounded cavities in portions of the dielectric layers having the faster etch rate. The rounded cavities extend horizontally into the sidewalls of the trench. A doped polysilicon layer is then formed on the top of the dielectric layers so as to fill the trench and the rounded cavities.

Abstract: A magnetic field enhanced plasma etch reactor system for generating a radially-directed magnetic field within a reaction chamber. The reactor system comprises a reaction chamber for containing a plasma and a plurality of electromagnetic coils disposed about a reaction region within the reaction chamber. When each coil is driven with a current of similar magnitude, the electromagnetic coils produce a radially-directed magnetic field within the reaction chamber. The radially-directed magnetic field uniformly distributes the plasma throughout a bulk plasma region. Consequently, a substrate that is etched by such a uniform plasma has an improved uniformity in the etch pattern on the substrate.

Abstract: A plasma discharge apparatus formed with a plasma chamber in which discharge is carried out wherein use is made, as the discharge gas sealed in the plasma chamber, of a mixed gas represented by Ne.sub.100-x Ar.sub.x A.sub.y (wherein, A is Ar, Kr, and/or Xe, x is 10 to 30 percent by volume, and y is 1 to 10 percent by volume). Note that when Kr and Xe are included as A, it is preferable that the Kr be included in an amount of 1 to 5 percent by volume and the Xe in an amount of 1 to 5 percent by volume.

Abstract: A method of manufacturing a capacitor for use in semiconductor memories is disclosed herein. The present invention includes forming a silicon oxide layer as an etching mask to etch a polysilicon layer to form a bottom storage node of a capacitor. The silicon oxide layer is formed from the thermal annealing of oxygen doped dot silicon.

Abstract: A method of manufacturing a capacitor for use in semiconductor memories is disclosed herein. The present invention includes forming anti-oxidizing regions from dot silicon for use as an oxidation mask to oxidize a polysilicon layer. Further, a silicon oxide layer is used as an etching mask to form a bottom storage node of a capacitor. An etching process is performed to etch a portion of the first polysilicon layer. Next, the silicon oxide layer is removed to define the bottom storage node. Utilizing the bottom storage node structure, the present invention can be used to increase the surface area of the capacitor.

Abstract: An apparatus for processing at least a surface of an article with a uniform plasma includes a processing chamber in which the article is disposed and a plasma source. The plasma source includes a dielectric plate having a first surface forming part of an inner wall of the processing chamber, and an electrical energy source, including a radiofrequency source and a substantially planar induction coil, the latter of which is disposed on a second surface of the dielectric plate, and to which energy from the radiofrequency source is preferably supplied through impedance matching circuitry. The substantially planar induction coil has at least two spiral portions which are symmetrical about at least one point of the substantially planar induction coil, and preferably forming a continuous "S-shape".

Abstract: An improved method for fabricating self-aligned contacts in a planar insulating layer to the source/drain contact areas on field effect transistors (FETs), formed in part from a first polycide layer, is achieved using an undoped polysilicon layer as an etch-stop layer. The planar insulating layer provides a good surface for patterning a second polycide layer without intralevel shorts that would otherwise occur over a rough topography. This is of particular use for forming the array of bit lines over the array of word lines for DRAM circuits. The method involves providing a patterned undoped polysilicon layer on the gate electrodes. A planarized insulating layer, such as reflowed borophosphosilicate glass (BPSG) is then deposited and reflowed to fill the high aspect ratio recesses between the closely spaced word lines.

Abstract: A process for fabricating multi-level semiconductor ROM devices is disclosed. Each memory cell of the ROM device can be programmed to any of three possible conduction states including full-conduction, half-conduction and no-conduction. The fabrication process begins with a semiconductor silicon substrate. Buried bit and word lines are formed in the substrate. A photomask is then formed to correspond to code to be programmed into the ROM device. The photomask, when properly aligned over the ROM device, contains portions that fully cover the entire channel region of a cell to be programmed for full conduction, portions that partially cover the channel regions of cells that are to be programmed for half-conduction, and portions that do not cover at all the channel regions of cells to be programmed for no-conduction. Then ions are implanted with the photomask in place. The ions transform the regions not covered or partially covered by the photomask.

Abstract: A method for fabricating a dual-gate oxide for memory with embedded logic has been achieved. The method is described for forming a thin gate oxide for the peripheral circuits on a DRAM device, while providing a thicker oxide for the memory cells having a boosted word line architecture. The method avoids applying photoresist directly to the gate oxide, and thereby prevents contamination. A first gate oxide is formed on the device areas on the substrate. A first polysilicon layer is deposited and patterned leaving portions over the memory cell areas. The first gate oxide is removed over the peripheral device areas, and is replaced by a thinner second gate oxide. A second polysilicon layer is deposited and patterned to remain over the peripheral device areas. The first and second polysilicon layers, having essentially equal thicknesses, are coated with an insulating layer.

Abstract: A method is disclosed to form memory cell structures for DRAMs in which the capacitor nodes are formed in the shape of posts that fit in an area no larger than that which is over the active regions of the semiconductor substrate. Hence, the posts are suitable to accommodate the area that is appropriate for any one of the very high density DRAMs up to and including 1 G-bit. Furthermore, one less mask is used to form the node electrode in comparison with prior art. The interior of said post structure constitutes one electrode and the exterior wall the other, while a thin dielectric separates the two polysilicon plates of the capacitor. It is shown that said post structures perform the multi-function of providing a good support during the planarization process. Optional pillars may be formed at judiciously chosen locations in the cell to provide additional storage nodes and/or more uniform support structures to more readily facilitate chemical-mechanical polishing (CMP) of the substrate surface.