Abstract: Various embodiments of the present disclosure are directed towards a trench capacitor with a trench pattern for yield improvement. The trench capacitor is on a substrate and comprises a plurality of capacitor segments. The capacitor segments extend into the substrate according to the trench pattern and are spaced with a pitch on an axis. The plurality of capacitor segments comprises an edge capacitor segment at an edge of the trench capacitor and a center capacitor segment at a center of the trench capacitor. The edge capacitor segment has a greater width than the center capacitor segment and/or the pitch is greater at the edge capacitor segment than at the center capacitor segment. The greater width may facilitate stress absorption and the greater pitch may increase substrate rigidity at the edge of the trench capacitor where thermal expansion stress is greatest, thereby reducing substrate bending and trench burnout for yield improvements.

Abstract: A semiconductor device includes a landing pad and a capacitor disposed on and electrically connected to the landing pad. The capacitor includes a cylindrical bottom electrode, a dielectric layer and a top electrode. The cylindrical bottom electrode is disposed on an in contact with the landing pads, wherein an inner surface the cylindrical bottom electrode includes a plurality of protruding portions, and an outer surface of the cylindrical bottom electrode includes a plurality of concaved portions. The dielectric layer is conformally disposed on the inner surface and the outer surface of the cylindrical bottom electrode, and covering the protruding portions and the concaved portions. The top electrode is conformally disposed on the dielectric layer over the inner surface and the outer surface of the cylindrical bottom electrode.

Abstract: An integrated circuit includes a first semiconductor well contained in a semiconductor substrate and a second semiconductor well contained in the first semiconductor well. A capacitive element for the integrated circuit includes a first electrode and a second electrode, where the first electrode includes at least one vertical conductive structure filling a trench extending vertically into the first semiconductor well. The vertical conductive structure is electrically isolated from the first semiconductor well by a dielectric envelope covering a base and the sides of the trench. The vertical conductive structure penetrates into the second semiconductor well at least at one longitudinal end of the trench. The second electrode includes the first semiconductor well and the second semiconductor well.

Abstract: A semiconductor device includes a substrate provided with a decoupling capacitor and plurality of circuit elements disposed along a first direction, and a plurality of first wiring line patterns disposed in a first wiring line layer over the substrate, including a power routing pattern coupled to the decoupling capacitor and a plurality of internal wiring line patterns coupled to the plurality of circuit elements. The plurality of first wiring line patterns extend in the first direction, and are aligned in conformity with virtual wiring line pattern tracks which are defined at a first pitch along a second direction intersecting the first direction and parallel to the substrate.

Abstract: A field effect transistor (FET) device is provided. The device includes an isolation region on a support substrate that separates a first back gate from a second back gate, and a gate dielectric layer on a first channel region and a second channel region. The device further includes a conductive gate layer having a work function value and a ferroelectric layer on the gate dielectric layer, wherein the first back gate can adjust a threshold voltage for the first channel region, and the second back gate can adjust a threshold voltage for the second channel region.

Abstract: A method for fabricating a MOMCAP includes steps as follows: An Nth metal layer is formed on a substrate according to an Nth expected capacitance value of the Nth metal layer. An Nth capacitance error value between an Nth actual capacitance value of the Nth metal layer and the Nth expected capacitance value is calculated. An N+1th expected capacitance value of an N+1th metal layer is adjusted to form an N+1th actual capacitance value according to the Nth capacitance error value, and the N+1th metal layer with an N+1th actual capacitance value is formed on the Nth metal layer according to the adjusted N+1th expected capacitance value, to make the sum of the Nth actual capacitance value and the N+1th actual capacitance value equal to the sum of the Nth expected capacitance value and the N+1th expected capacitance value. N is an integer greater than 1.

Abstract: An electrostatic discharge (ESD) protection device may be provided, including a substrate having a conductivity region arranged therein, a first terminal region and a second terminal region arranged within the conductivity region, and a field distribution structure. The field distribution structure may include an intermediate region arranged within the conductivity region between the first terminal region and the second terminal region, an isolation element arranged over the intermediate region, and a first conductive plate and a second conductive plate arranged over the isolation element. The first conductive plate may be electrically connected to the first terminal region and the second conductive plate may be electrically connected to the second terminal region.

Abstract: A semiconductor package includes a semiconductor chip and a redistribution layer structure. The redistribution layer structure is arranged to form an antenna transmitter structure and an antenna receiver structure over the semiconductor chip, wherein patterns of the antenna receiver structure are located at different levels of the redistribution layer structure, and at least one pattern of the antenna transmitter structure is at the same level of the topmost patterns of the antenna receiver structure.

Abstract: A display device including a lower substrate, a display structure, pad electrodes, and a driver integrated circuit. The lower substrate has a display area and a pad area. The display structure is disposed in the display area on the lower substrate. The pad electrodes are disposed in the pad area on the lower substrate while being spaced apart from each other in a first direction. The driver integrated circuit is spaced apart from the pad electrodes in the second direction in the pad area on the lower substrate, and includes a circuit portion and a first blocking portion spaced apart from the circuit portion in a second direction perpendicular to the first direction.

Abstract: Some embodiments of the disclosure provide a semiconductor device. The semiconductor device comprises: a substrate; a first nitride semiconductor layer on the substrate; a second nitride semiconductor layer on the first nitride semiconductor layer and having a band gap larger than a band gap of the first nitride semiconductor layer; an intermediate layer disposed on the second nitride semiconductor layer; and a conductive structure disposed on the intermediate layer, wherein a first even interface is formed between the intermediate layer and the second nitride semiconductor layer.

Abstract: A semiconductor device and a method of forming the same are provided. The method includes forming a sacrificial gate structure over an active region. A first spacer layer is formed along sidewalls and a top surface of the sacrificial gate structure. A first protection layer is formed over the first spacer layer. A second spacer layer is formed over the first protection layer. A third spacer layer is formed over the second spacer layer. The sacrificial gate structure is replaced with a replacement gate structure. The second spacer layer is removed to form an air gap between the first protection layer and the third spacer layer.

Abstract: Disclosed herein are quantum dot devices, as well as related computing devices and methods. For example, in some embodiments, a quantum processing device may include a quantum well stack, the quantum well stack includes a quantum well layer, the quantum processing device further includes a plurality of gates above the quantum well stack to control quantum dot formation in the quantum well stack, and (1) gate metal of individual gates of the array of gates is tapered so as to narrow farther from the quantum well stack or (2) top surfaces of gate metal of individual gates of the array of gates are dished.

Abstract: Semiconductor devices and methods of forming the same are provided. A semiconductor device according to the present disclosure includes a ferroelectric structure including a channel region and a source/drain region, a gate dielectric layer disposed over the channel region of the ferroelectric structure, a gate electrode disposed on the gate dielectric layer, and a source/drain contact disposed on the source/drain region of the ferroelectric structure. The ferroelectric structure includes gallium nitride, indium nitride, or indium gallium nitride. The ferroelectric structure is doped with a dopant.

Abstract: A semiconductor package using a coreless signal distribution structure (CSDS) is disclosed and may include a CSDS comprising at least one dielectric layer, at least one conductive layer, a first surface, and a second surface opposite to the first surface. The semiconductor package may also include a first semiconductor die having a first bond pad on a first die surface, where the first semiconductor die is bonded to the first surface of the CSDS via the first bond pad, and a second semiconductor die having a second bond pad on a second die surface, where the second semiconductor die is bonded to the second surface of the CSDS via the second bond pad. The semiconductor package may further include a metal post electrically coupled to the first surface of the CSDS, and a first encapsulant material encapsulating side surfaces and a surface opposite the first die surface of the first semiconductor die, the metal post, and a portion of the first surface of the CSDS.

Abstract: A method of manufacturing a semiconductor package is provided and includes forming a protective layer on a passivation layer and a connection pad of a semiconductor chip exposed by a first opening of the passivation layer, forming an insulating layer on the protective layer, forming a via hole penetrating the insulating layer to expose the protective layer, forming a second opening by removing a portion of the protective layer through the via hole, and forming a connection via filling the via hole and the second opening and a redistribution layer on the connection via. The second opening and the via hole are connected to have a stepped portion. The first opening has a width narrower closer to the connection pad, and the second opening has a width wider closer to the connection pad.

Abstract: A system on a chip (SOC) device includes a substrate, processing circuitry formed on the substrate, and noise reduction circuitry formed on the processing circuitry. The noise reduction circuitry is configured to reduce noise caused by variations in current consumed by the processing circuitry. The noise reduction circuitry includes a decoupling capacitor, which includes (i) two or more first layers, (ii) one or more second layers interleaved between the first layers, (iii) dielectric layers formed between adjacent first and second layers and configured to electrically isolate between the adjacent first and second layers, (iv) a first contact, which is electrically connected to the first layers so as to form a first electrode of the decoupling capacitor, and (v) a second contact, which is electrically connected to the second layers so as to form a second electrode of the decoupling capacitor.

Abstract: A display device includes a substrate, a circuit layer on the substrate, a display layer on the circuit layer, at least one hole in a display area of the substrate that penetrates the substrate, the circuit layer, and the display layer, and at least two grooves that surround the at least one hole, where each of the at least two grooves has an undercut structure. The substrate includes a first substrate, a first inorganic layer, a second substrate, and a second inorganic layer, which are sequentially stacked, and each of the at least two grooves extends down from the display layer into the second substrate.

Abstract: Semiconductor devices and methods of forming the same are provided. In one embodiment, a semiconductor device includes a contact feature in a first dielectric layer, a first passivation layer over the contact feature, a bottom conductor plate layer disposed over the first passivation layer and including a first plurality of sublayers, a second dielectric layer over the bottom conductor plate layer, a middle conductor plate layer disposed over the second dielectric layer and including a second plurality of sublayers, a third dielectric layer over the middle conductor plate layer, a top conductor plate layer disposed over the third dielectric layer and including a third plurality of sublayers, and a second passivation layer over the top conductor plate layer.

Abstract: Disclosed herein are quantum dot devices, as well as related computing devices and methods. For example, in some embodiments, a quantum dot device may include: a quantum well stack including a quantum well layer; a first gate above the quantum well stack, wherein the first gate includes a first gate metal; and a second gate above the quantum well stack, wherein the second gate includes a second gate metal, and a material structure of the second gate metal is different from a material structure of the first gate metal; wherein the quantum well layer has a first strain under the first gate, a second strain under the second gate, and the first strain is different from the second strain.

Abstract: A display device includes: a second wiring layer on the first insulating film, the second wiring layer overlapping with a part of the first pad portion, the second wiring layer including a second pad portion not overlapping with the first line portion; an etching-stop layer overlapping with at least a boundary between the first pad portion and the first line portion; a second insulating film covering the second wiring layer, the second insulating film having a contact hole, the contact hole including a first area where the second insulating film, the first insulating film, and the first pad portion are penetrated, the contact hole including a second area where the second insulating film is penetrated and the second pad portion is a bottom; and a third wiring layer inside the contact hole, the third wiring layer connected to the first pad portion and the second pad portion.