Abstract: A semiconductor structure includes a conductive structure over a first passivation layer; and a second passivation layer over the conductive structure and the first passivation layer. The second passivation layer has a first oxide film extending along a top surface of the first passivation layer, sidewalls and a top surface of the conductive structure, wherein a top surface of the first oxide film is planar. The second passivation layer further includes a second oxide film over a top surface of the first oxide film and a top surface of the conductive structure, wherein a top surface of the second oxide film is planar. The second passivation layer further includes a third oxide film extending along a top surface of the second oxide film, the sidewalls and the top surface of the conductive structure, wherein a top surface of the third oxide film is curved.

Abstract: Standardized photon building blocks are used to make both discrete light emitters as well as array products. Each photon building block has one or more LED chips mounted on a substrate. No electrical conductors pass between the top and bottom surfaces of the substrate. The photon building blocks are supported by an interconnect structure that is attached to a heat sink. Landing pads on the top surface of the substrate of each photon building block are attached to contact pads disposed on the underside of a lip of the interconnect structure. In a solder reflow process, the photon building blocks self-align within the interconnect structure. Conductors on the interconnect structure are electrically coupled to the LED dice in the photon building blocks through the contact pads and landing pads. The bottom surface of the interconnect structure is coplanar with the bottom surfaces of the substrates of the photon building blocks.

Abstract: According to an embodiment, a structure includes a substrate including a semiconductor material, wherein the substrate is provided with one or more recesses each of which has a depth direction that is equal to a thickness direction of the substrate, and the one or more recesses include a sidewall on which a plurality of grooves each extending in the depth direction are provided.

Abstract: A method for forming a semiconductor structure includes forming a gate electrode layer over a semiconductor substrate, forming a first spacer layer to cover a sidewall of the gate electrode layer, recessing the first spacer layer to expose an upper portion of the sidewall of the gate electrode layer, forming a metal material to cover an upper surface and the upper portion of the sidewall of the gate electrode layer; reacting a semiconductor material of the gate electrode layer with the metal material using an anneal process to form a silicide layer, and removing the metal material after the anneal process.

Abstract: A light emitting device includes a substrate and a light emitting element mounted on the substrate, a light transmissive member, covering member, first and second protruding members, and a protective element. The light transmissive member is disposed on an upper surface of the light emitting element. The covering member covers an upper surface of the substrate, a lateral surface of the light emitting element, and at least a portion of a lateral surface of the light transmissive member such that an upper surface of the light transmissive member is exposed. The first protruding member and the second protruding member are provided on the substrate such that the light emitting element and the light transmissive member are positioned between the first protruding member and the second protruding member. The protective element is mounted on the substrate so as to be positioned between the light emitting element and the second protruding member.

Abstract: A light emitting element includes: a semiconductor structure including: a first semiconductor, an active layer, and a second semiconductor layer; a first electrode; a first insulating layer; a first internal electrode; a second internal electrode; a second insulating layer; a first external electrode; and a second external electrode.

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a transistor with an embedded isolation layer in a bulk substrate and methods of manufacture. The structure includes: a bulk substrate; an isolation layer embedded within the bulk substrate and below a top surface of the bulk substrate; a deep trench isolation structure extending through the bulk substrate and contacting the embedded isolation layer; and a gate structure over the top surface of the bulk substrate and vertically spaced away from the embedded isolation layer, the deep trench isolation structure and the embedded isolation layer defining an active area of the gate structure in the bulk substrate.

Abstract: The present invention provides a manufacturing method of a semiconductor device and a semiconductor device. A semiconductor device is provided, the semiconductor device includes a substrate, a stacked structure disposed on the substrate, the substrate comprises a cell array region, a peripheral circuit region and a middle region between the cell array region and the peripheral circuit region, a first trench located in the middle region, a second support layer located on an upper surface of the stacked structure, wherein parts of the second support layer is disposed in the first trench, and a capacitor structure located in the cell array region.

Abstract: A low-profile packaging structure for a microelectromechanical-system (MEMS) resonator system includes an electrical lead having internal and external electrical contact surfaces at respective first and second heights within a cross-sectional profile of the packaging structure and a die-mounting surface at an intermediate height between the first and second heights. A resonator-control chip is mounted to the die-mounting surface of the electrical lead such that at least a portion of the resonator-control chip is disposed between the first and second heights and wire-bonded to the internal electrical contact surface of the electrical lead.

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to virtual bulk in semiconductor on insulator technology and methods of manufacture. The structure includes a heterojunction bipolar transistor formed on a semiconductor on insulator (SOI) wafer with a doped sub-collector material in a buried insulator region under a semiconductor substrate of the SOI wafer.

Abstract: A semiconductor device including a first substrate and a thin film transistor disposed on the first substrate is provided. The thin film transistor includes a gate, a semiconductor pattern, a first insulating layer, a source and a drain. The first insulating layer is disposed between the gate and the semiconductor pattern. The source and the drain are separated from each other and disposed corresponding to the semiconductor pattern. At least one of the source and the drain has a first copper patterned layer and a first copper oxynitride patterned layer. The first copper oxynitride patterned layer covers the first copper patterned layer. The first copper patterned layer is disposed between the first copper oxynitride patterned layer and the first substrate. Moreover, a manufacturing method of the semiconductor device is also provided.

Abstract: A semiconductor device includes a semiconductor substrate having a surface perpendicular to the first direction; a vertical Hall element formed in the semiconductor substrate, and including a magnetosensitive portion having a depth in the first direction, a width in the second direction, and a length in the third direction; and an excitation wiring extending in the third direction and disposed above the semiconductor substrate and at a position that overlaps the center position of the width of the magnetosensitive portion, and the value u derived from Expression (1) is 0.

Abstract: Present disclosure provide a capacitor includes: a semiconductor substrate; a laminated structure including n conductive layers and m dielectric layer(s), the i-th conductive layer being provided with at least one i-th isolation trench, the (i+1)-th conductive layer being provided above the i-th conductive layer and in the i-th isolation trench, isolation trenches in odd-numbered and even-numbered conductive layers having a first and a second overlap region in a vertical direction respectively, and the first overlap region not overlapping the second overlap region, where m, n, and i are positive integers, n?2, and 1?i?n?1; at least one first external electrode electrically connected to all odd-numbered conductive layer(s) through a first conductive via structure in the second overlap region; and at least one second external electrode electrically connected to all even-numbered conductive layer(s) through a second conductive via structure in the first overlap region.

Abstract: An electronic device includes a ferroelectric layer arranged on a channel region and a gate electrode arranged on the ferroelectric layer. The ferroelectric layer includes a plurality of first oxide monolayers and a second oxide monolayers that is arranged between the substrate and the gate electrode and include a material different from a material of the first oxide monolayers. The first oxide monolayers include oxide monolayers that are alternately formed and include materials different from one another.

Abstract: A semiconductor device includes a semiconductor die, an N-doped region, an N-contact metal, a PN junction mesa, a P-contact metal, a first passivation layer, an anode feed metal, and a cathode feed metal. The semiconductor die may include a plurality of semiconductor layers disposed on an insulating substrate. The N-doped region may define an active area of the device. The N-contact metal may be disposed on a first portion of the N-doped region. The PN junction mesa may be disposed on a second portion of the N-doped region. The PN junction mesa may comprise a hyperabrupt N-doping layer disposed on the first portion of the N-doped region and a P-doped layer disposed on the hyperabrupt N-doping layer. The P-contact metal may be disposed on the P-doped layer of the PN junction mesa. The first passivation layer may cover the semiconductor layers of the semiconductor device and have openings for the N-contact metal and the P-contact metal. The anode feed metal may connect the P-contact metal to a first bond pad.

Abstract: The present disclosure relates to a display panel including a display area that can be stretched by including a plurality of stretching units and a peripheral area positioned at an edge of the display area. Each of the stretching units includes: a plurality of islands separately disposed to include a plurality of pixels disposed therein; a plurality of bridges extended from the islands to connect adjacent islands or to connect the islands with the peripheral area; and a plurality of openings disposed adjacent to the bridges, between the bridges, and between the bridges and the islands, wherein areas of the islands are gradually increased toward the peripheral area.

Abstract: An object is to provide a semiconductor device with large memory capacity. The semiconductor device includes first to seventh insulators, a first conductor, and a first semiconductor. The first conductor is positioned on a first top surface of the first insulator and a first bottom surface of the second insulator. The third insulator is positioned in a region including a side surface and a second top surface of the first insulator, a side surface of the first conductor, and a second bottom surface and a side surface of the second insulator. The fourth insulator, the fifth insulator, and the first semiconductor are sequentially stacked on the third insulator. The sixth insulator is in contact with the fifth insulator in a region overlapping the first conductor. The seventh insulator is positioned in a region including the first semiconductor and the sixth insulator.

Abstract: A semiconductor memory device includes a conducting layer and an insulating layer that are disposed above a semiconductor substrate, a plurality of pillars that extend in a direction which crosses a surface of the semiconductor substrate, and a plate that is disposed between the plurality of pillars and extends in the same direction as the pillars. A surface of the plate, which faces the pillars, has convex portions and non-convex portions.

Abstract: A package manufacturing process and semiconductor packages are provided. An interposer having a crystal structure is provided. A first die and a second die are bonded on the interposer. The second die is positioned to be spaced apart from the first die with a gap extending direction that is perpendicular to a shortest distance of the gap, and the gap extending direction is not parallel with a crystallographic orientation of the crystal structure of the interposer. A molding compound is formed over the interposer covering the first and second dies. The molding compound and the interposer are cut into packages.

Abstract: The present application discloses a semiconductor device with a landing pad of conductive polymer and a method for fabricating the semiconductor device. The semiconductor device includes a substrate, a dielectric layer disposed over the substrate, a plug disposed in the dielectric layer, and a landing pad of conductive polymer disposed over the dielectric layer. The method includes: providing a substrate; forming a dielectric layer with a plug over the substrate; performing an etching process to remove a portion of the dielectric layer to expose a protruding portion of the plug; forming a conductive polymer layer covering the dielectric layer and the protruding portion; and performing a thermal process to form a landing pad over the dielectric layer in a self-aligned manner. The landing pad of conductive polymer comprises a protruding portion of the plug, a first silicide layer disposed over the protruding portion, and a second silicide layer disposed on a sidewall of the protruding portion.