Abstract: An ordinary read/write operation (normal operation) and a refresh operation are separated from one another and the number of read amplification circuits or, in other words, the number of sense amplifiers operating during the normal operation is made smaller than that during the refresh operation. Accordingly, a bit line charge/discharge current during the normal operation can be reduced.

Abstract: A system of Flash EEprom memory chips with controlling circuits serves as non-volatile memory such as that provided by magnetic disk drives. Improvements include selective multiple sector erase, in which any combinations of Flash sectors may be erased together. Selective sectors among the selected combination may also be de-selected during the erase operation. Another improvement is the ability to remap and replace defective cells with substitute cells. The remapping is performed automatically as soon as a defective cell is detected. When the number of defects in a Flash sector becomes large, the whole sector is remapped. Yet another improvement is the use of a write cache to reduce the number of writes to the Flash EEprom memory, thereby minimizing the stress to the device from undergoing too many write/erase cycling.

Abstract: The semiconductor memory device includes two sense amplifiers provided corresponding to data lines and a switching circuit for selectively connecting any two among the data lines to the two sense amplifiers, respectively. The data stored in one of the memory cells is amplified to be transmitted to an output buffer via the data line connected to one of the sense amplifiers. In parallel with this operation, the data stored in a next memory cell is amplified via the data line connected to another sense amplifier so as to be made valid. In this manner, after the data stored in one of the memory cell is transmitted to the output buffer, the data stored in the next memory cell is subsequently transmitted to the output buffer.

Abstract: A static random-access memory (SRAM) of late-write type, in which the total time required to write data is reduced, thereby increasing the write margin. No time is therefore wasted in writing and reading data. The SRAM has an address register for holding a write address, besides an address register for holding an input address. A pass gate selects the write address held in the address register or the input address held in the address register. In a read cycle, a decoding path is formed to decode a read address, without using delay circuits. In a write cycle, a second decoding path is formed to decode a write address, using delay circuits. In the cycle preceding the first write cycle coming after the operating mode of the SRAM is switched from the read mode to the write mode, a third decoding path is formed to decode the write-address signal read from the address register. The first, second and third decoding paths are controlled by pass gates.

Abstract: The present invention is a system and method which allows random programming and avoids the problem with band-to-band tunneling current discussed above. In particular, the present invention applies a predetermined voltage along the wordlines adjacent to the programming wordline. A method of programming in a Flash memory system includes providing a first wordline coupled with a first device desired to be programmed, the first wordline also coupled with a second device desired to be program inhibited; electrically isolating the second device; programming the first device; and programming a third device coupled with a second wordline, the second wordline not being adjacent to the first wordline.

Abstract: In an address transition detecting circuit, signal conversion detecting circuits output complementary time difference signals which are inverted in response to potential level changes of corresponding address lines respectively. Waveform shaping one-shot pulse generating circuits receive corresponding complementary time difference signals and output one-shot pulse signals of prescribed time widths. A waveform composing circuit outputs an ATD signal of a prescribed pulse length in response to activation of any one-shot pulse signal. Therefore, the lengths of the one-shot pulses outputted from the waveform shaping one-shot pulse generating circuits remain unchanged even if the potential level of any signal line is abruptly converted, and an ATD signal of a constant pulse length is regularly outputted.

Abstract: An improved semiconductor memory device and a data writing method thereof capable of preventing semiconductor memory breakage and written data error which occur when data are predominantly written on a certain address by evenly writing the data on each address of a memory device, which includes a data region for writing a data; and a counter region for counting the number that a data is written on the data region.

Abstract: An integrated circuit comprising a reference voltage generator having an output providing a reference voltage; a selectively engageable filter having an input connected to the output of the reference voltage generator, and having an output; a voltage regulator having an input connected to the output of the filter, and having an output; a dynamic random access memory receiving power from the output of the voltage regulator, the dynamic random access memory having memory cells that are accessed or refreshed in response to a first signal; and a timing circuit which engages the filter in response to presence of a first signal, and causes the filter to filter the reference voltage.

Abstract: A sense amplifier (2) is connected to an input/output circuit (7), transmitting input/output data therebetween. The input/output circuit (7) is connected to an address scramble circuit (8). Furthermore, the input/output circuit (7) is connected to a data input/output terminal (DIO), externally transmitting data. The address scramble circuit (8) receives input data (INTDQ) from the data input/output terminal (DIO) and converts the input data (INTDQ) into write data (WD) in accordance with the layout of memory cells in a memory array (1) in response to a burn-in mode signal (BIT) outputted from an address key circuit (9) and a row address first signal RAF outputted from a row address buffer (6). Having the above configuration, a semiconductor memory device can be provided, which permits a prescribed stress to be imposed on its internal circuit only by inputting simple data even in a burn-in test.

Abstract: An apparatus identifies redundancy memory cells that are selected to replace defective memory cells of a memory matrix that communicates with a data bus. A redundancy address register is associated with one of the redundancy memory cells. The redundancy address register stores a default state until it is programmed with an address of one of the defective memory cells. A control circuit generates a test signal during an identification mode. A detect circuit is coupled to the control circuit and to the redundancy address register and generates a default-detect signal in response to the test signal when the redundancy address register contains the default state. A data-bus multiplexer that is coupled to the redundancy-cell selection circuit, the data bus, and the control circuit couples the default detect signal to the data bus in response to the test signal.

Abstract: A signal input buffer attains a through state when an external clock signal Ka is in an inactive state and generates an internal signal in response to an external signal, and attains a latch state when the external clock signal is in an inactive state. Data transfer from a master data register which stores data in an DRAM array through a slave data register is executed in response to a detection of the slave data register of being in use. The slave data register stores data to be transferred to an SRAM array or data to be externally accessed. Thus, a synchronous semiconductor memory device accessible at a high speed and with no wait is provided. In addition, internal clock signal is activated for a predetermined time in response to activation of an external clock signal to secure a precise internal operating timing.

Abstract: A memory array (25) having a selected memory cell (10) and an unselected memory cell (30) is programmed and read. Each memory cell in the memory array (25) contains an isolation transistor (22) and a floating gate transistor (23). To program the selected memory cell (10), programming voltages are applied to a control gate line (21), a drain line (14), an isolation line (19), and a source line (12). To reduce the effects of the drain disturb problem, a gate terminal (32) of the unselected memory cell (30) is held at a positive voltage. To read selected memory cell (10), a read voltage is applied to an isolation gate line (31) of unselected memory cell (30) which insures that the unselected memory cell (30) does not conduct or contribute to leakage current and power consumption during the read operation.

Abstract: A semiconductor memory device includes a memory cell array having a plurality of memory cells arranged in rows and columns, a plurality of pairs of bit lines to each of which the plurality of memory cells arranged in the column direction are connected, a plurality of latch type amplifiers each of which is provided between the bit lines of a corresponding one of the bit line pairs to amplify a potential difference between the bit lines, a plurality of activation circuits for respectively activating the plurality of latch type amplifiers, a data bus acting as passages of input data, a plurality of latch type storage circuits each of which is provided on a corresponding one of the columns and connected to the data bus, for temporarily storing the input data, a plurality of transfer gates for transferring the input data from the latch type storage circuits to the latch type amplifiers, and a transfer control circuit for controlling the transfer gates to simultaneously transfer the input data from the latch type s

Abstract: A single-port RAM generator architecture, for the generation of different RAM structures in a CAD environment, and to test the operation capabilities of the different RAM structure, The architecture includes a Static RAM matrix and a self timed architecture, which includes a control logic, both a dummy row and a dummy column having respectively equivalent load of a word line and of bit column of said matrix. The dummy column is discharged at a faster rate than the corresponding bit column optimizing the timing and reducing power consumption. Different column multiplexer selections provide different RAMs for a selected RAM size, each having slightly different silicon area and timing performance.

Abstract: In a semiconductor memory cell array including word lines, bit lines, and a plurality of memory cells arranged at crossings between the word lines and the bit lines, the bit lines are grouped into odd and even numbered groups. A shift redundancy circuit is arranged between each group of odd or even bit lines and sense amplifier and write circuits for the purpose of shifting a defective memory cell to a redundant memory cell.

Abstract: During a period corresponding to the former half of one cycle of a clock signal, a capacitor is charged to an intermediate potential between the respective precharged potentials of two level-shifters. Subsequently, during a period corresponding to the latter half of one cycle of the clock signal, the capacitor is connected to that one of the output nodes which shifts to a lower potential in the level-shifter on the upper stage, while a power source line is connected to the other output node which shifts to a higher potential. On the other hand, the capacitor is also connected to that one of the output nodes which shifts to the higher potential in the level-shifter on the lower stage, while the ground line is connected to the other output node which shifts to the lower potential. Consequently, there can be provided a semiconductor integrated circuit free from power dissipation that might have been caused by an internal power-source circuit.

Abstract: In a data write apparatus to a flash electrically erasable programmable read only memory (EEPROM) built in a microcomputer which is mounted on a circuit board, a write control section first initializes the flash EEPROM to allow data to be written in the flash EEPROM, and supplies a signal indicative of the data for the flash EEPROM. A level converting section convertes a level of the data signal such that the data signal level matches to an actual operation voltage level of the flash EEPROM and supplies the converted data signal to the flash EEPROM such that the data is written in the flash EEPROM.

Abstract: A memory device includes an address decoder, a global data line, and a plurality of memory blocks, which are each coupled to the address decoder and the global data line. Each memory block includes a plurality of column lines, a local data line, and a plurality of memory cells that are arranged in columns and are each coupled to a corresponding one of the column lines. Each memory block also includes or has associated therewith a switching circuit that is coupled to the column lines and the local data line. The switching circuit couples a selected column line to the local data line and couples the local data line to the global data line when the memory block is selected. The switching circuit uncouples each of the column lines from the local data line when the memory block is unselected, or during a read cycle when the memory block is selected and the sense-amplifier is enabled.

Abstract: An address buffer for high speed static random-access-memory (SRAM) devices is disclosed. The address buffer includes a buffer stage, an out-phase variable buffer circuit and an in-phase variable buffer circuit. The buffer stage includes a number of series-connected buffer units for transmitting an input address signal. The out-phase variable buffer circuit is connected to the buffer stage for providing a first buffer condition in a write period and for providing a second buffer condition in a read period. The in-phase variable buffer circuit is also connected to the buffer stage for providing a third buffer condition in the write period and for providing a fourth buffer condition in the read period. An external address signal can be delayed by the various buffer conditions of the address buffer during the write period to optimize the operation of the SRAM devices, and the various buffer conditions will not affect the read period.

Abstract: A P-channel MOS memory cell has P+ source and drain regions formed in an N-well. A thin runnel oxide is provided between the well surface and an overlying floating gate. In one embodiment, the thin tunnel oxide extends over a substantial portion of the active region and the device. An overlying control gate is insulated from the floating gate by a first insulating layer. An overlying select gate is insulated from the control gate by an insulating layer. The select gate includes an elongated extension portion for preventing overprogramming of the circuit. The device is programmed via hot electron injection from the drain end of the channel region to the floating gate, without avalanche breakdown, which allows the cell to be bit-selectable during programming. Erasing is accomplished by electron tunneling from the floating gate to the N-well with the source, drain, and N-well regions equally biased.