Abstract: Wordline driver circuitry drives a plurality of wordlines in a flash EEPROM memory array in a first mode which selects between a positive voltage and ground, and a second mode which selects between a negative voltage and ground. A first supply voltage selector supplies positive voltage during the first mode, and a second mode reference voltage, such as ground, in the second mode. A second supply voltage selector supplies the first mode reference voltage such as ground in the first mode, and the negative voltage during a second mode. An inverting driver has an input which receives a wordline select signal, and an output coupled to the wordline, a first supply voltage input connected to the first supply voltage selector, and second supply voltage input connected to the second supply voltage selector.

Abstract: A system and method is disclosed for increasing read performance of domino SRAMS. A conventional word-line, which drives two transistors per cell, is replaced with two separate word-lines. The first word-line drives one transistor and the second word-line drives the other transistor. The first word-line is used to write zeros into cells, while the second word line is used to both write ones into cells and to read the contents of the cells. Since the second word-line drives only one transistor during read operations, one-half of the gate load on the writeead word-line is eliminated.

Abstract: In a ferroelectric memory, when data is read out from a memory cell, for the purpose of minimizing a variation of the voltage on the pair of data signal lines caused by factor other than the current caused due to the polarization of the ferroelectric capacitor, the number of memory cells connected to each one data signal line is limited. Thus, a voltage not smaller than the coercive voltage can be applied between the opposing electrodes of the ferroelectric capacitor, with the result that a sufficient read-out signal voltage can be obtained.

Abstract: A ferroelectric gate transistor has a structure in which n-type source and drain regions are formed on a p-type semiconductor, a ferroelectric thin film is formed on a channel region between the source and drain regions, and a gate electrode is formed thereon. Memory information is erased by applying a voltage V.sub.g to the ferroelectric to cause poling in the first direction. The memory information is written by applying a voltage V.sub.W lower than a coercive voltage of the ferroelectric and having a polarity opposite to that of the voltage V.sub.g to the ferroelectric. The memory information is read out by applying a voltage V.sub.DR lower than the voltage V.sub.W and having a polarity opposite to that of the voltage V.sub.g to the drain to read a drain current I.sub.DS.

Abstract: An integrated circuit memory device has two banks of NAND structured memory cells and a clock input for synchronously latching control, address and data signals. Time delays of sequentially accessing and restoring memory bits in the NAND structure are masked through the use of the dual bank architecture and synchronous timing. The NAND structured memory cells provide an extremely dense memory array for a high capacity memory device. The input clock signal driving a synchronous word line generator provides a simplified high speed access to the array. A set of random access storage registers temporarily store data from the array and provide high speed page access to an entire page of data from each bank of the memory. The ability to access one bank while simultaneously opening or closing a row in the other bank allows for an unlimited number of high speed sequential data accesses.

Abstract: A memory cell for a programmable logic device (PLD) and method for programming the memory cell. The memory cell includes components typically found in a memory cell for a PLD including an NMOS transistor having a floating gate, and two capacitors coupled to the floating gate, one capacitor being a tunneling capacitor enabling charge to be added to and removed from the floating gate. The memory cell further includes an NMOS pass gate transistor for supplying charge to the tunneling capacitor, but unlike conventional NMOS pass gates, it has a reduced threshold so that during programming when a programming voltage is applied to its drain, it can be turned on with an identical programming voltage applied to its gate, rather than requiring that its gate voltage be pumped above its drain voltage during programming. The reduced threshold can be obtained by removing the vt implant and punch through implant normally provided in its channel, or by other means.

Abstract: A very small computer memory card is densely packed with a large number of flash EEPROM integrated circuit chips. A computer memory system provides for the ability to removably connect one or more of such cards with a common controller circuit that interfaces between the memory cards and a standard computer system bus. Alternately, each card can be provided with the necessary controller circuitry and thus is connectable directly to the computer system bus. An electronic system is described for a memory system and its controller within a single memory card. In a preferred physical arrangement, the cards utilize a main circuit board with a plurality of sub-boards attached thereto on both sides, each sub-board carrying several integrated circuit chips.

Abstract: A first transistor is connected between an external power supply and an output node. To increase a voltage of the output node up to a boost voltage, the first transistor is first turned on in response to a first signal and then increases the voltage of the output node up to a voltage of the external power supply. A second transistor is connected between a booster circuit and the output node and turned on in response to a second signal after a lapse of a predetermined period of time after the first signal to increase the voltage of the output node up to the boost voltage. A third transistor is connected between the output node and ground and turned on in response to a third signal when the voltage of the output node is equal to a ground potential.

Abstract: In a semiconductor memory device, a power supply voltage detecting circuit receives a power supply voltage for outputting a detection signal which is activated when the power supply voltage is not higher than a reference level and which is deactivated when the power supply voltage is higher than a reference level, and a voltage step-up circuit receives the power supply voltage for supplying a stepped-up voltage. A voltage selection circuit receives the power supply voltage and the stepped-up voltage and is controlled by the detection signal to supply the stepped-up voltage to a word line of the memory when the detection signal is active and the power supply voltage to the word line of the memory when the detection signal is inactive.

Abstract: About 10 drive pulses, each having a predetermined positive potential of +3 V and a predetermined negative potential of -10 V, are applied to the control gate of a memory cell transistor. This drive pulse is generated in a semiconductor device on the basis of an original signal supplied from an external signal generator. By arranging the signal generator outside the semiconductor device, an increase in the necessary area of a semiconductor pellet is prevented.

Abstract: A dual-port memory having an on-chip color register for storage of input data for use in multiple write cycles is disclosed. The color register is written to during a special cycle, which is enabled by a special function pin in conjunction with the write enable and transfer enable function pins, each of which have their logic state latched in during the row address strobe signal. A second type of special cycle causes a multiplexer to select the contents of the color register, rather than the latched data state of the data input terminals, for the data to be written to the selected memory cells. The use of the color register may be used in conjunction with a mask register, where the writing of certain input/outputs is inhibited. In addition, a block write feature may be incorporated with the color register so that, in another type of special cycle, multiple columns per input/output can be simultaneously written with the contents of the color register.

Abstract: A memory is described which can successively perform a plurality of functions during one row access cycle. A reallocation circuit and method are provided to "hand off" the multi-port memory strobe operation from the row access strobe input to either the column access strobe input or an optional strobe circuit. By reallocating the strobe operation, combinations of functions can be performed without the need to close the accessed row. The memory can isolate at least two internal memory circuits after preforming a transfer of data therebetween. The memory can thereby randomly access newly transferred data without the need to close the accessed row where the data is located.

Abstract: A defective cell repairing circuit for repairing a defective cell in a packaged semiconductor memory device enables repair mode operations for mapping an address of a detected defective cell to a redundant cell. The address of the defective cell is programmed by selectively cutting fuses corresponding to each bit of the defective cell address. The defective cell address programming operation uses input terminals on the packaged semiconductor memory device which are used for address signals in a normal operation mode, so that no additional pins are required. Repair mode operations are prevented after the repair mode is completed. Thereafter, an external address supplied to the semiconductor memory device is compared with the programmed defective cell address determined by the state of the fuses, and a redundant cell is selected if the two addresses correspond.

Abstract: A semiconductor memory device is provided which can apply a voltage stress to every adjacent bit lines even when data is written using a data bit compression function in a burn-in test mode. More specifically, when data is written using the data bit compression function in the test mode, an input buffer circuit is brought to a state in which it receives a signal corresponding to a signal dq0 applied to a specific input/output terminal by a switch circuit controlled by a test mode specify signal TE in common. When an inversion designate signal INV is in an active state, a complementary signal corresponding to a signal obtained by inversion of signal dq0 by an inverting circuit is output to internal data buses IO0, ZIO0, and IO2, ZIO2. On the other hand, a complementary signal corresponding to signal dq0 is output to internal data buses IO1, ZIO1, and IO3, ZIO3.

Abstract: Dummy information of a third level, which is between first and second levels written in a plurality of memory cells, is written in a dummy memory cell from a source node through transistors. Thus, a potential difference is caused between a read bit line and a dummy read bit line in reading. A potential comparison circuit indicates the level of information read from any memory cell on the basis of the comparison result as to the potentials of the dummy read bit line and the read bit line. Thus, the read rate is increased, the read operation is stabilized and increase of the chip area is suppressed.

Abstract: A digital value on a plurality of control input terminals of a PCMCIA power multiplexer integrated circuit determines which one if any of a plurality of power input terminals (for example, 12 volts, 5 volts, and 3 volts) is coupled through the integrated circuit to a power output terminal. A decoder which decodes the digital value prevents any two of the power input terminals from being coupled to the power output terminal at the same time. The decoder is programmable so that a single power multiplexer integrated circuit die layout can support a variety of PCMCIA controllers outputting different digital values. The integrated circuit has current limit, controlled power turn on times, and overtemperature protection. A signal indicative of a fault condition (for example, an overtemperature or a current limit condition) is output onto a fault output terminal of the integrated circuit.

Abstract: A static RAM includes: a memory cell array including word lines, bit line pairs and memory cells; a row recorder; a column decoder; a DTD signal generator responsive to transition of input data or transition of a write enable signal for generating a data transition detection signal for a prescribed time period; and a write driver responsive to the write enable signal and the data transition detection signal for supplying the input data to a bit line pair selected by the column decoder. Even when there is a noise in write enable signal during reading cycle and data transition detection signal is generated erroneously, erroneous writing of data can be prevented, since write enable signal is not supplied to the write driver.

Abstract: A semiconductor device includes a first battery BAT 1; a second battery BAT 2; and switches SW1, SW2, SW3, and SW4. Switching block 13 is provided for switching a power source for backing up a memory 3 to retain data. Also a voltage comparator 5 is provided for comparing an external power supply voltage supplied by the power supply VCC of a host apparatus with a reference voltage Vref. In response to the signal from a main battery presence sensor block for sensing the presence of the first battery BAT 1 and the signal from the voltage comparator 5, the memory 3 is backed up to retain data by the external power supply voltage when it is supplied, and further, the second battery BAT 2 is charged by a charging circuit 6 driven by the external power supply voltage. When neither external power supply voltage nor first battery BAT 1 is present, the second battery BAT 2 backs up the memory 3 to retain data.

Abstract: A semiconductor memory device includes a sense amp band including a plurality of sense amplifiers, and a plurality of operation power supply potential lines and a plurality of ground potential lines arranged in a meshed shape. The operation power supply potential lines and the ground potential lines include the lines arranged in parallel with and in proximity to the sense amp band. Each sense amplifier in the sense amp band is connected to an operation power supply potential line and a ground line arranged in proximity to and in parallel with the sense amplifier through a drive component. The drive component is provided one for a predetermined number of sense amplifiers, and is rendered conductive in response to a sense amplifier activation signal from a signal line arranged in parallel with the sense amp band. The plurality of operation power supply potential lines and the plurality of ground lines arranged in a meshed shape are contacted at crossings.

Abstract: A read line for a column of memory cells within an array is divided into a first read line segment, a first read buffer, and a second read line segment. Both the first and second read line segments occupy a single wiring channel. When reading a memory cell connected to the first read line segment, the level of the first read line segment is sensed by the first read buffer and conveyed to a column read output node by way of the second read line segment and an associated second read buffer. Alternatively, when reading a memory cell connected to the second read line segment, the first read buffer is disabled, thus adopting a high impedance output, and the level of the second read line segment is sensed by the second read buffer and conveyed to the column read output node. Each of the first and second read line segments have less capacitive loading than a single read line, which results in lower power and faster read access times.