Abstract: The disclosed device can be used to accelerate the tests carried out on memories by using a row and column address generator normally designed for operations of pre-erasure programming of the memory. The working in test mode is determined by a test word. During a test, row and/or column counters of the generator are selectively incremented by an incrementation signal given by a control unit that performs a pre-erasure programming operation. Application notably to FLASH EEPROM memories and the integrated circuits that incorporate these memories.

Abstract: A voltage level detection circuit is disclosed. The circuit is incorporated into a dynamic memory, integrated onto a single semiconductor substrate to which external voltage and reference potentials are applied. The dynamic memory contains an array of memory cells and circuitry for writing and reading information into and from the cells of the array. It contains an oscillator for generating an oscillator signal when the external voltage is above the reference potential. The voltage level detection circuitry is controlled by the oscillator signal, for controlling a voltage obtained from the external voltage, to the reading and writing circuitry and to the array to prevent the voltage from being applied unless the voltage is a lease of a predetermined minimum value. It may contain a circuit for sampling the obtained voltage during selected oscillator cycles to determine whether the obtained voltage is above the predetermined value. Other elements may be added to further enhance performance of the circuit.

Abstract: A dynamic memory comprises a control circuit for controlling the selection of the row decoder and the activation of the sense amplifiers in accordance with a RAS signal externally supplied thereto and a word line control circuit for controlling a selected word line to turn the electric potentials read out from the memory cells connected to the word line on the bit lines connected to the respective memory cells back to an inactive level after the electric potentials are sensed and amplified by the sense amplifiers corresponding to the respective bit lines during the time period from the time when the RAS signal is turned to an active level and the time when it is turned back to the inactive level. A dynamic memory has gate oxide films are designed to be subjected to a less electric field strength in order to minimize the degradation of reliability and the memory can effectively reduce the fall of the word line driving stepped-up voltage to eliminate the necessity of a leak current compensation circuit.

Abstract: There is provided non-volatile semiconductor memory a capable of performing an accurate program verify, by suppressing the power supply noise generated at the time of a program verify. An output buffer includes a mode discriminating circuit for discriminating an ordinary reading mode and a programming mode, and a load circuit. Connection/disconnection of the load circuit is determined by a NOR gate receiving a verify activation signal which is activated at the time of verify, in such a manner that the load circuit is put in a disconnected condition at the time of the ordinary reading, and in a connected condition at the time of the program verify.

Abstract: A data register that stores the data corresponding to the selected memory cell in a memory cell array is provided near the memory cell array. A decoder that selects the data from the data register starts decoding in response to an address signal accessing the memory cells in synchronization with a clock signal determining the operation period. In the first half of an operation period of the clock signal, the decoder outputs a signal in response to a signal corresponding to the address signal determined in the preceding operation period. According to the output of the decoder, the data register is selected. In the latter half of the operation period, a signal corresponding to a new address signal for the next operation period is transferred to the decoder. By doing this, the output control signal in the decoder is caused to synchronize with a signal driving an address signal, enabling the proper address to be selected without fail.

Abstract: A pair of thin film transistors formed in adjacent layers of polysilicon. The gate of the first TFT and the source, drain and channel regions of the second TFT are formed in the first polysilicon layer. The source, drain and channel regions of the first TFT and the gate of the second TFT are formed in the second polysilicon layer. A dielectric layer is interposed between the first and second polysilicon layers. The first TFT gate overlaps the second TFT drain region in the first polysilicon layer and the second TFT gate overlaps the first TFT drain region in the second polysilicon layer. In another aspect of the invention, two TFTs are incorporated into a SRAM memory cell.

Abstract: The present invention may provide a control circuit for controlling a number of output buffer circuits coupled to memory cells for outputting the read out data of the memory cells according to the address translation detection signal, wherein the control circuit causes about a half of the output buffer circuits to be set high level and the remaining output buffer circuits to be set low level.

Abstract: The sequential-access asynchronous memory device comprises an asynchronous double-port random access memory (MVDP), a write address generator (CE) for delivering to the input port of the memory, in response to write enable signals (ATE), successive write address information (ADE) respectively associated with successive data (DE) to be stored sequentially in a predetermined order of writing, a read address generator (CL) for delivering to the output port of the memory, in response to read enable signals (ATL), successive read address information (ADL) respectively associated with successive data (DL) to be read sequentially in a predetermined order of reading, a device for detecting the stability of the address information delivered by the address generators, and a device (GAE, GAL, ST1, ST2) for determining the level of fill of the memory from the stable address information delivered by the address generators.

Abstract: A random access memory circuit is described which uses single ferroelectric memory cells to store data. The ferroelectric memory cells can be selectively read using reference cells to generate a reference voltage which is compared to a voltage representative of data stored on the memory cell using a multiplexed sense amplifier. In using two ferroelectric reference cells in which one contains a logical 0 polarization, and the other contains a logical 1 polarization, a single-ended reference voltage can be generated on a reference bit line. A ferroelectric memory cell can then be read by comparing the voltage on its corresponding bit line to the reference bit line using the sense amplifier. The content of the memory cell being read and the content of the reference cells can be rewritten on the same clock cycles to save on access time.

Abstract: A memory circuit (14) having features specifically adapted to permit the memory circuit (14) to serve as a video frame memory is disabled. The memory circuit (14) contains a dynamic random access memory array (24) with buffers (18, 20) on input and output data ports (22) thereof to permit asynchronious read, write and refresh accesses to the memory array (24). The memory circuit (14) is accessed both serially and randomly. An address generator (28) contains an address buffer register (36) which stores a random access address and an address sequencer (40) which provides a stream of addresses to the memory array (24). An initial address for the stream of addresses is the random access address stored in the address buffer register (36).

Abstract: A word line driver circuit (10) for driving four word lines (18) is disclosed. In a preferred embodiment, the word line driver circuit (10) includes a decoder circuit (12) for pulling a decode node (20) to a logic low level (Vss) in response to internal row decode signals, a pull-up circuit (14) for pulling the decode node (20) to a logic high (Vcc) to deselect the word lines (18), four transfer transistors (NO) intermediate the decode node (20) and four control nodes (22), four CMOS inverters (18), each driving one word line (18) between a boost voltage and Vss. A PMOS level shifter transistor (P0) is associated with each inverter (18), and has a channel width that is small relative to both the channel widths of the transfer transistors (N0) and to the devices making up the decoder circuit (12), allowing the level shifter transistors (P0) to be overpowered by the decoder circuit (12).

Abstract: A semiconductor memory device includes a sense amplifier and a load circuit which are connected to a pair of data buses through which cell data is read. The sense amplifier produces an output data signal in accordance with voltage potentials of transfer signals on the data buses. During data reading operation of the memory device, the sense amplifier is enabled and the transfer signals on the data buses have a different voltage potential level from each other. The load circuit sets the data buses at a predetermined reset voltage potential in a stand by state of the data reading operation. The reset voltage potential is intermediate of the voltage potential levels of the data buses when the sense amplifier is enabled.

Abstract: A method and apparatus for evaluating a memory having memory elements and redundant memory elements for redundancy replacement. The redundant memory elements are tested to determine the number of good redundant memory elements. The memory elements are also tested to determine whether there are any failing memory elements. It is then determined whether a sufficient number of good redundant elements are available to replace the failing memory elements. If an insufficient number of redundant memory elements are available, the testing is stopped.

Abstract: A semiconductor memory device has a plurality of memory cells in an array, into which the memory cells data is writable, and which can subsequently be read. Each memory cell has a switching element with one terminal connected to a bit line of the array another terminal connected to at least one ferroelectric capacitor, and a control terminal connected to a word line. The cell may then be operated to detect the change in polarization of the ferroelectric capacitor when a voltage is applied which is not sufficient to cause a change of state of the ferroelectric capacitor. Alternatively, a ferroelectric capacitor and a capacitor other than a ferroelectric capacitor is connected to the switching element. In a further alternative, a plurality of ferroelectric capacitors are connected to the switching element, so that different data are writable into each.

Abstract: A semiconductor memory, such as, of a dual-port type includes dynamic RAM cells, such as of the single-transistor, single-capacitor type in which each such cell is coupled to one data line of a corresponding pair of data lines and a word line. The memory has a plurality of sense amplifiers which are coupled to a plurality of data line pairs, respectively, a plurality of pairs of switching MOSFETs respectively coupled between the plurality of data line pairs and a common data line pair for providing either selective or simultaneous connection of the plurality of data line pairs to the common data line during a first write mode and a second write mode, respectively.

Abstract: An improved multi-bit memory cell includes a storage capacitor and a switching element coupled to one of the terminals of the capacitor. The switching element includes a first switching component having a positive threshold, and a complementary switching component having a negative threshold. Because the switching element is constructed in this manner, noise generation caused by activation of the switching components is significantly reduced, and cut-off effects are eliminated. Both of these factors contribute to the memory cell's ability to store more bits of information than prior art memory cells.

Abstract: The drain of a memory cell transistor is connected to a sub bit line of an EEPROM. The sub bit line is connected to a main bit line via the drain-source path of a selection transistor. The equivalent capacitance of the sub bit line is precharged to the potential of the main bit line when the selection transistor is temporarily turned on. The potential of the precharged sub bit line tends to drop in the presence of a leakage current component equivalent resistance. However, when the selection transistor is intermittently turned on by using pulses to supply charges from the main bit line to the sub bit line, a drop in sub bit line potential can be prevented.

Abstract: Any one of the internal circuits of a semiconductor integrated circuit is made to operate both at a relatively high operating voltage having a predetermined allowable range and at a relatively low operating voltage also having a predetermined allowable range. The operating voltage is supplied from the outside. Moreover, the operating conditions of the internal circuits constituting the semiconductor integrated circuit are individually set restrictive to the relatively high operating voltage having a predetermined allowable range and to the relatively low operating voltage having a predetermined allowable range. The semiconductor integrated circuit is made to operate selectively at these operating voltages. Since the internal circuits are operated at these two kinds of operating voltages, an arrangement of internal circuits can be simplified and at the same time the semiconductor integrated circuit is usable in not only the conventional system but also a low-voltage one.

Abstract: A method and structure for controlling the timing of an access to a DRAM array in response to a row access (RAS#) signal and the rising and falling edges of a clock signal. Row address decoding and the deactivation of equalization circuits are initiated when the row access signal is received and a rising edge of the clock signal is detected. The row address decoding and the deactivation of the equalization circuits are completed before the falling edge of the clock signal occurs. The falling edge is then used to initiate the turning on of the sense amplifiers of the DRAM array. The sense amplifiers are turned on before the subsequent rising edge of the clock signal. The subsequent rising edge is then used to initiate the column address decoding operation of the DRAM array. A test mode is included which allows the DRAM array to be operated asynchronously for testing purposes.

Abstract: A system and method for improving a domino SRAM that eliminates the need for additional transistors in series with evaluation transistors. The regular structure inherent in RAM arrays is used to minimize both the effective recharge cycle time and the recharge power required to recharge the various levels of domino SRAM circuits. Using a clock signal as a reference, recharge signals are timed to each other and to other functional signals. By adjusting buffers and wiring delays associated with each recharge signal, the recharge signals sent to each level of logic are delayed until the recharge of the previous level is complete.