Abstract: Dynamic voltage frequency scaling to transition to a target clock frequency and associated target voltage is provided. Dynamic voltage frequency scaling to a different clock frequency is performed by gradually changing the clock frequency using discrete variable-size steps, while dynamically switching to faster or slower reference clock frequencies as appropriate to harmonize the frequency trajectory with system requirements.

Abstract: Methods for calibrating antenna oscillators are provided including initiating a clock offset process from a primary antenna with a remote antenna within a radio frequency (RF) range of the primary antenna to determine a clock offset between the primary antenna and the remote antenna; calculating a temperature difference between a primary temperature of the primary antenna and a temperature of the remote antenna; and instructing the remote antenna to adjust a clock frequency of the remote antenna based on the determined clock offset and the calculated temperature.

Abstract: A digitally controlled oscillator (DCO) circuit is disclosed. The DCO circuit comprises a tuning circuit configured to tune an oscillation frequency of the DCO circuit based on processing an integer tuning codeword and a fractional tuning codeword associated with an input tuning codeword. In some embodiments, the tuning circuit comprises an integer tuning circuit configured to process the integer tuning codeword and a fractional tuning circuit configured to process the fractional tuning codeword, in order to implement the input tuning codeword. In some embodiments, the integer tuning codeword comprises an integer tuning range associated therewith and the fractional tuning codeword comprises a fractional tuning range associated therewith. In some embodiments, the fractional tuning range associated with the fractional tuning codeword is configured to cover more than one step of the integer tuning range associated with the integer tuning codeword.

Abstract: An oscillator circuit powered by a source voltage generates an oscillating output signal. The oscillating output signal is level shifted and applied to a first input of a multiplexer. A second input of the multiplexer receives the oscillating output signal. The multiplexer selects one of the oscillating output signal and the level shifted oscillating output signal for output as a selected oscillating output signal in response to a select signal. A locked loop circuit generates controls a frequency of the oscillating output signal as a function of the selected oscillating output signal and a reference oscillating signal. The select signal further selects one of a reference voltage and the source voltage of the oscillator circuit as an error amplifier reference voltage for a voltage regulator circuit that generates the first power supply voltage.

Abstract: A circuit device includes a processing circuit and an oscillation signal generation circuit. The processing circuit performs Kalman filter processing for a result of phase comparison between an input signal based on an oscillation signal and a reference signal and performs loop filter processing for the result of phase comparison. The oscillation signal generation circuit generates the oscillation signal of an oscillation frequency set by frequency control data which is output data of the loop filter processing by using the frequency control data and a resonator. The processing circuit estimates a truth value for an observed value of the result of phase comparison by using the Kalman filter processing.

Abstract: A method for a radar device is described. According to one example implementation, the method comprises generating an RF signal using a voltage-controlled oscillator (VCO), wherein the frequency of the RF signal depends on a first tuning voltage and a second tuning voltage. The method also comprises setting the second tuning voltage using a phase-locked loop coupled to the VCO, with the result that the frequency of the RF signal corresponds to a desired frequency. The first tuning voltage is changed in such a manner that the second tuning voltage set by the phase-locked loop corresponds approximately to a predefined value.

Abstract: A system and method for calibrating a pulse width modulation (PWM) signal that extends the on time by a higher resolution increment. The system comprises a PWM generator that receives a VDDIO rail to generate first and second PWM signals, the second PWM signal having an on time extended by the higher resolution increment having a commanded length. The system further comprises a VDDIO circuit that receives the VDDIO rail and outputs a VDDIO signal. First and second analog-to-digital converters are configured to generate a first and second sets of PWM samples and first and second sets of VDDIO samples. A microcontroller is configured to calculate an actual increment length based on the samples, and to compensate for a difference between the commanded length and the actual increment length.

Abstract: Examples described herein provide determining skew of transistors on an integrated circuit. In an example, an integrated circuit includes a ring oscillator and first and second detector circuits. The ring oscillator includes serially connected buffers. Each buffer includes serially connected inverters that include transistors. A transistor of each buffer has a different strength of another transistor of the respective buffer. The first and second detector circuits are connected to different first and second tap nodes, respectively, along the serially connected buffers. The first detector circuit is configured to count a number of cycles of a reference clock that a cyclic signal on the first tap node is either a logically high or low level. The second detector circuit is configured to count a number of cycles of the reference clock that a cyclic signal on the second tap node is either a logically high or low level.

Abstract: Certain aspects relate to a semiconductor die. The semiconductor die includes a voltage-controlled oscillator (VCO), wherein the VCO includes a resonant capacitor, and a resonant inductor coupled in parallel with the resonant capacitor. The resonant inductor includes a first elongated portion and a second elongated portion that are parallel with each other. The semiconductor die also includes a voltage supply line configured to route a supply voltage to the VCO, wherein the voltage supply line includes a first portion that runs parallel with the first and second elongated portions of the resonant inductor and is located between the first and second elongated portions of the resonant inductor.

Abstract: A filtering circuit for filtering a pulse width modulated (PWM) signal includes a D flip-flop having an input terminal configured to be coupled to a logic high signal and having an output terminal coupled to an output terminal of the filtering circuit; and a circuit coupled between an input terminal of the filtering circuit and the D flip-flop, the circuit configured to, for a first pulse of the PWM signal having a duty cycle within a pre-determined range: generate a positive pulse at a clock terminal of the D flip-flop as a clock signal of the D flip-flop; and generate a negative pulse at a reset terminal of the D flip-flop as a reset signal of the D flip-flop, wherein a duration between a rising edge of the positive pulse and a falling edge of the negative pulse is equal to a duration of the first pulse of the PWM signal.

Abstract: A circuit includes a first ring oscillator with a plurality of stages, each coupled via a voltage follower cross-coupling to a plurality of stages of a second ring oscillator. Further ring oscillators may be coupled to the first ring oscillator and the second ring oscillator. Additionally, the voltage follower cross-coupling for each of the stages may include one or more first voltage follower having a first strength, and one or more second voltage follower having a second strength different than the first strength.

Abstract: Methods of making a semiconductor device packages may involve placing a metal material at least partially around a region of integrated circuitry embedded within an active surface of a semiconductor die, the metal material located on the active surface. At least a portion of the metal material may be left electrically disconnected from the region of integrated circuitry. The semiconductor die and the metal material may be encapsulated in an encapsulant material, the encapsulant material extending to a height above the active surface higher than a maximum height of the metal material above the active surface.

Abstract: In one form, an analog-to-digital converter (ADC) includes first and second ring-oscillator ADCs, a modulus subtractor, and a decimation filter. The first and second ring-oscillator ADCs are responsive to true and complement input voltages, respectively, have outputs for providing first and second digital phase signals, respectively, each having a first predetermined number of bits sampled at a first frequency. The modulus subtractor subtracts the second digital phase signal from the first digital phase signal to provide a phase difference signal. The decimation filter differentiates the phase difference signal at a second frequency lower than said the frequency to provide a frequency signal proportional to a differential voltage between the true input voltage and the complementary input voltage, and decimates the frequency signal to provide a digital code having a second predetermined number of bits greater than the first predetermined number of bits.

Abstract: A power system including a rectifier and an inverter. The rectifier has a plurality of phase input terminals and a plurality of rectifier output terminals that provide respective rectified outputs, rectifier circuitry that rectifies the signals on the phase input terminals to generate respective rectified outputs on the rectifier output terminals, a rectifier neutral to receive a power source neutral, and capacitors connected between the rectifier neutral and the rectifier output terminals. The inverter includes a respective plurality of inverter input terminals respectively connected to the rectifier output terminals, a plurality of inverter output terminals, and an inverter neutral. The rectifier neutral and the inverter neutral are coupled by a conductor to form a same neutral.

Abstract: In described examples, a first clock generator generates an output clock signal in response to an input reference signal and in response to a feedback signal that is generated in response to the output clock signal. A code generator generates a code in response to the input reference signal. A loss detector generates an indication of a loss of the input reference signal in response to the feedback signal and at least two codes generated by the code generator.

Abstract: A frequency synthesis device with high multiplication rank, including a base frequency generator generating two first base signals of square shape of same frequency and opposite to each other, a first synthesis stage including two first switching power supply oscillators, of which the power supplies are respectively switched by the two first base signals, a second synthesis stage including a second switching power supply oscillator of which the supply is switched by a combination of the output signals of the two first oscillators, the output of the second switching power supply oscillator being filtered by a frequency discriminator circuit realized with an injection locked oscillator.

Abstract: In described examples, an apparatus includes: at least one resonant circuit for receiving a radio frequency signal; a rectifier coupled to the resonant circuit to output a first rectified signal with a constant level portion and a portion matching a first portion of the radio frequency signal, and to output a second rectified signal having a constant level portion and a portion that matches a second portion of the radio frequency signal; a first limiter circuit to limit a voltage of the first rectified signal to a predetermined maximum voltage level; a second limiter circuit to limit the voltage of the second rectified signal to the predetermined maximum voltage level; a third limiter circuit to limit a voltage of the first rectified signal to a predetermined minimum voltage level; and a fourth limiter circuit to limit the voltage of the second rectified signal to the predetermined minimum voltage level.

Abstract: A phase-locked loop (PLL) for generating a VCO output signal at a target frequency has been disclosed. The PLL includes at least first and second VCOs, first and second multiplexers, and a frequency divider. The first and second VCOs generate first and second output signals over first and second frequency ranges, respectively. The first multiplexer receives the first and second output signals from the first and second VCOs, respectively, and outputs the first output signal when the target frequency is in the first frequency range and the second output signal when the target frequency is in the second frequency range or less than the first frequency range. The frequency divider divides a frequency of the second output signal by a division factor to generate a third output signal. The second multiplexer outputs one of the first, second, and third output signals as the VCO output signal.

Abstract: New wireless power transmission techniques are disclosed. In some aspects of the invention, a system distributes wireless power from a power and information transmitting base station, through a network of intermediate wireless power enhancement and consumption devices, each of which may be independently owned and controlled. The system may assign invoices comprising monetary credits and debits, based on each device's use or enhancement of the wireless power provided through the network. Other power storage and transmission techniques are also disclosed, including a new form of universal battery, with variable space-filling aspects and a central battery core with improved, flexibly-applied contacts.

Abstract: A second-order ?? modulator includes a plurality of integrators and a parallel higher-bit processing part, and the parallel higher-bit processing part includes a plurality of addition and determination processing sections. The addition and determination processing section receives first and second carry inputs and first and second state inputs, and outputs a quantized output and first and second state outputs. A first selector selects one set from sets of the first and the second state outputs from the plurality of addition and determination processing sections and outputs the selected set, and a second selector selects one quantized output from the quantized outputs from the plurality of addition and determination processing sections. An output of the first selector is used as a selection control signal for the first and the second selectors.