Patents Examined by Joseph Chang
  • PLL with Lock-in Frequency Controller
    Patent number: 10693480
    Abstract: A PLL has a frequency comparator that is active during lock-in. It outputs a signal related to the difference between the oscillator frequency and a target frequency. It captures an initial phase and observes change in phase relative to the initial phase. Two ways of capturing the initial phase are provided. The frequency comparator can provide input signals for the loop filter and make the PLL act as a frequency-locked loop during lock-in. Alternatively, it can provide input signals for a search controller that may perform a binary or other search. The frequency comparator may wait one or more cycles of the reference clock signal to reduce noise, or it may set a threshold to eliminate some noise. It may signal that the oscillator frequency equals the target frequency when the threshold has not been exceeded after a timeout. The search controller may directly or indirectly control the PLL's oscillator.
    Type: Grant
    Filed: May 15, 2019
    Date of Patent: June 23, 2020
    Inventor: Julian Jenkins
  • Circuit device, oscillator, electronic apparatus and vehicle
    Patent number: 10686457
    Abstract: A circuit device includes an oscillation signal generation circuit for generating an oscillation signal with an oscillation frequency set by frequency control data, and a processing circuit. The processing circuit includes a counter for performing a count process based on the oscillation signal, and a latch circuit for holding a count value of the counter based on a reference signal. The processing circuit performs a loop filter process on a phase comparison result based on output data of the latch circuit to output the frequency control data, holds information based on the phase comparison result when the holdover is detected, and outputs the frequency control data based on the information held, in a holdover period.
    Type: Grant
    Filed: May 15, 2019
    Date of Patent: June 16, 2020
    Assignee: SEIKO EPSON CORPORATION
    Inventor: Kentaro Seo
  • Atomic oscillator and frequency signal generation system
    Patent number: 10680629
    Abstract: An atomic oscillator includes a light emitting element, an atomic cell, and a light receiving element that receives the light passing through the atomic cell. The atomic cell has a first chamber containing alkali metal atoms in a gas state and having a first wall through which the light from the light emitting element passes, a second chamber containing alkali metal atoms in a liquid state and having a second wall, a passage connecting the first chamber and the second chamber to each other, and a part which is disposed between the first chamber and the second chamber and has a thermal conductivity lower than the thermal conductivity of a material forming the first wall and the thermal conductivity of a material forming the second wall.
    Type: Grant
    Filed: April 26, 2019
    Date of Patent: June 9, 2020
    Assignee: Seiko Epson Corporation
    Inventors: Koji Chindo, Nobuhito Hayashi, Hideaki Yajima
  • Time-to-digital converter, circuit device, physical quantity measurement apparatus, electronic instrument, and vehicle
    Patent number: 10678190
    Abstract: A time-to-digital converter includes a first oscillation circuit that starts oscillating at the transition timing of a first signal and generates a first clock signal having a first clock frequency, a second oscillation circuit that starts oscillating at the transition timing of a second signal and generates a second clock signal having a second clock frequency, a first adjustment circuit that adjusts the oscillation frequency of the first oscillation circuit based on a reference clock signal, a second adjustment circuit that adjusts the oscillation frequency of the second oscillation circuit based on the reference clock signal, and a processing circuit that converts the time difference between the transition timing of the first signal and the transition timing of the second signal into a digital value based on the first and second clock signals.
    Type: Grant
    Filed: August 28, 2018
    Date of Patent: June 9, 2020
    Assignee: Seiko Epson Corporation
    Inventor: Yasuhiro Sudo
  • Method and associated signal system improving mitigation of injection-pulling effect
    Patent number: 10680626
    Abstract: The invention provides method and associated signal system improving mitigation of injection-pulling effect for an oscillator which generates an output clock under control of a control signal. The method may include: by a loop filter, filtering a deviation signal to form a filtered signal; by a SIL (self-injection locked) controller, forming an auxiliary signal which tracks the deviation signal or a phase difference between a reference clock and an output signal resulting from the output clock; and, forming the control signal by summing the filtered signal and the auxiliary signal.
    Type: Grant
    Filed: September 4, 2018
    Date of Patent: June 9, 2020
    Assignee: MEDIATEK INC.
    Inventors: Chieh-Hsun Hsiao, Shih-Chi Shen, Chi-Hsueh Wang, Hsin-Hung Chen
  • Multi-ring cross-coupled voltage-controlled oscillator
    Patent number: 10673443
    Abstract: Two rings of a voltage controlled oscillator (VCO) configured to generate a plurality of phases of an oscillator signal, each ring of the two rings comprising three stages of inverters configured to generate a subset of phases of the plurality of phases of the oscillator signal, cross coupled via each stage to a corresponding stage in an other ring of the two rings using inverters to inverse-phase lock the subsets of phases of the plurality of phases of the oscillator signal of the two rings, and configured to receive inputs at each stage from a previous stage in the ring and a feed-forward signal from a successive stage in the other ring of the two rings, and a tail current supply configured to supply the two rings of the VCO with a tail current, the tail current comprising a low-magnitude proportional component and a high-magnitude integral component.
    Type: Grant
    Filed: April 8, 2019
    Date of Patent: June 2, 2020
    Assignee: KANDOU LABS, S.A.
    Inventors: Abdelsalam Ahmed Hassanin, Kiarash Gharibdoust, Milad Ataei Ashtiani
  • Moving object detection circuit and method thereof
    Patent number: 10673444
    Abstract: A moving object detection circuit for detecting movement information of a measured object. The moving object detection circuit includes a mixing circuit, an analog-to-digital conversion circuit, a mixing unit, and a distance detecting unit. The mixing circuit mixed the RF carrier signal and a first analog signal to generate a second analog signal. The first analog signal is generated by a signal reflected from the measured object. The analog-to-digital conversion circuit coupled to the mixing circuit for generating a digital signal according to the second analog signal. The mixing unit mixed an IF signal and a first/second IF carrier signal to generate a first/second signal. The distance detecting unit generated a detection result according to the first signal and the second signal. The detection result is corresponding to a distance between the measured object and the moving object detection circuit.
    Type: Grant
    Filed: April 25, 2019
    Date of Patent: June 2, 2020
    Assignee: RichWave Technology Corp.
    Inventor: Hsiang-Feng Chi
  • Active CMOS recovery units for wireless power transmission
    Patent number: 10673351
    Abstract: A rectifying circuit includes, in part, first and second NMOS transistors, an impedance matching network, and an RF block circuit. The source and gate terminals of the first NMOS transistor respectively receive the ground potential and a biasing voltage. The second NMOS transistor has a gate terminal coupled to the drain terminal of the first NMOS transistor, a drain terminal coupled to the gate terminal of the first NMOS transistor, and a source terminal receiving the ground potential. The impedance matching network is disposed between the antenna and the drain terminals of the first and second NMOS transistors. The RF block circuit is coupled between the drain terminals of the first and second NMOS transistors and the output terminal of the rectifying circuit. The RF block circuit is adapted to prevent the RF signal from flowing into the output terminal of the rectifying circuit.
    Type: Grant
    Filed: June 8, 2018
    Date of Patent: June 2, 2020
    Assignee: CALIFORNIA INSTITUTE OF TECHNOLOGY
    Inventors: Seyed Ali Hajimiri, Behrooz Abiri, Florian Bohn
  • System and method for very low frequency detection of an event signature
    Patent number: 10666273
    Abstract: A system includes a very low frequency (VLF) antenna connected to a circuit that has a high pass filter and a low pass filter. The circuit is configured for noise reduction and frequency localization of detected VLF signals. A receiver is configured to receive filtered VLF signals output by the circuit and to separate desired signals for processing. A display is configured to provide a user with visual feedback based at least in part on an even signature extracted by a digital signal processor (DSP).
    Type: Grant
    Filed: January 9, 2019
    Date of Patent: May 26, 2020
    Assignee: United States of America as represented by Secretary of the Navy
    Inventors: Oren Sternberg, John Rockway, Mitchell Lerner, Israel Perez, Nicholas Lumsden
  • Compensation technique for the nonlinear behavior of digitally-controlled oscillator (DCO) gain
    Patent number: 10659057
    Abstract: Systems and methods are provided for hopping a digitally controlled oscillator (DCO) among a plurality of channels, wherein a gain of the DCO KDCO is a nonlinear function of frequency. A first normalized tuning word (NTW) corresponding to a first channel of the plurality of channels is generated. A first normalizing gain multiplier X is generated based on the nonlinear function of frequency, on an estimate of the nonlinear function of frequency, at a first frequency corresponding to the first channel. The first NTW is multiplied by the first X to obtain a first oscillator tuning word (OTW). The first OTW is input to the DCO to cause the DCO to hop to the first channel. A system for hopping among a plurality of channels at a plurality of respective frequencies comprises a phase-locked loop (PLL), a digitally controlled oscillator (DCO), a multiplexer, and an arithmetic module.
    Type: Grant
    Filed: August 21, 2018
    Date of Patent: May 19, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Chao Chieh Li, Min-Shueh Yuan, Robert Bogdan Staszewski, Chia-Chun Liao
  • Oscillating frequency wave grid generator
    Patent number: 10644649
    Abstract: An acoustic wave force field generator array that uses a plurality of synchronized oscillating emitters system that effectively blocks noise from passing through an acoustic barrier of wave/bubble pattern forms generated by the rapid oscillation of the integrated magnet and emitter system. The movement of the magnets also produces an EM field that generates a current to at least partially power the driver and speaker systems.
    Type: Grant
    Filed: June 11, 2018
    Date of Patent: May 5, 2020
    Assignee: Chromodynamics II LLC
    Inventor: Renee Marion Kastan Dahl
  • Oscillating circuitry
    Patent number: 10637486
    Abstract: The present disclosure relates to oscillating circuitry, comprising a controllable oscillator operable to generate an output signal having an output frequency dependent on a coarse value and a fine value, the coarse value causing the output frequency to be within an associated band of output frequencies and the fine value controlling the output frequency within that band; and control circuitry operable to generate the coarse and fine values so as to control the controllable oscillator. In certain arrangements, the control circuitry compensates for temperature fluctuations during operation.
    Type: Grant
    Filed: June 19, 2018
    Date of Patent: April 28, 2020
    Assignee: SOCIONEXT, INC.
    Inventor: Albert Hubert Dorner
  • Methods and apparatus to increase efficiency for wireless power transfer
    Patent number: 10637291
    Abstract: An example apparatus includes a feedback loop to: change a direction value when a second current value is greater than a first current value, the second current value being obtained after the first current value; and maintain the direction value when the second current value is less than the first current value. When the direction value corresponds to a first direction value, a summer increases a reference signal by a step size. When the direction value corresponds to a second direction value different than the first direction value, the summer decrease the reference signal by the step size.
    Type: Grant
    Filed: December 10, 2018
    Date of Patent: April 28, 2020
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Kosha Mahmodieh, Gianpaolo Lisi, Ali Djabbari, Jingwei Xu, Vijayalakshmi Devarajan
  • Oscillator circuit and associated oscillator device
    Patent number: 10630297
    Abstract: The present invention provides an oscillator circuit and associated oscillator device. The oscillator circuit comprises a negative-temperature-coefficient (NTC) bias current generating circuit and a set of oscillator sub-block circuits. The NTC bias current generating circuit is coupled between a supply voltage and a ground voltage, and is arranged to generate at least one NTC bias current. The set of oscillator sub-block circuits are coupled to each other to form an oscillator. Each oscillator sub-block circuit of the set of oscillator sub-block circuits comprises a plurality of transistors coupled between the supply voltage and a node within the NTC bias current generating circuit, wherein the NTC bias current generating circuit and the aforementioned each oscillator sub-block circuit share at least one transistor in the plurality of transistors.
    Type: Grant
    Filed: December 18, 2018
    Date of Patent: April 21, 2020
    Assignee: Artery Technology Co., Ltd.
    Inventors: Baotian Hao, Chao Li, Weitie Wang
  • Circuit device, oscillator, electronic apparatus, and vehicle
    Patent number: 10623003
    Abstract: A circuit device includes an A/D conversion circuit that performs an A/D conversion of a temperature detection voltage, a digital filter that performs digital filter processing of A/D output temperature detection data, a selector that selects A/D output temperature detection data during an activation period and selects filter output temperature detection data during a normal operation period after the activation period, a digital signal processing circuit that outputs frequency control data of an oscillation frequency based on selector output temperature detection data, and an oscillation signal generation circuit that generates an oscillation signal of an oscillation frequency set by frequency control data.
    Type: Grant
    Filed: November 16, 2018
    Date of Patent: April 14, 2020
    Assignee: Seiko Epson Corporation
    Inventor: Shinnosuke Kano
  • Power distribution architecture with series-connected bus converter
    Patent number: 10594223
    Abstract: Apparatus for power conversion are provided. One apparatus includes a power converter including an input circuit and an output circuit. The power converter is configured to receive power from a source for providing power at a DC source voltage VS. The power converter is adapted to convert power from the input circuit to the output circuit at a substantially fixed voltage transformation ratio KDC=VOUT/VIN at an output current, wherein VIN is an input voltage and VOUT is an output voltage. The input circuit and at least a portion of the output circuit are connected in series across the source, such that an absolute value of the input voltage VIN applied to the input circuit is approximately equal to the absolute value of the DC source voltage VS minus a number N times the absolute value of the output voltage VOUT, where N is at least 1.
    Type: Grant
    Filed: June 28, 2018
    Date of Patent: March 17, 2020
    Assignee: VLT, Inc.
    Inventors: Patrizio Vinciarelli, Andrew D'Amico
  • Locked loop circuit and method with digitally-controlled oscillator (DCO) gain normalization
    Patent number: 10594323
    Abstract: A locked-loop circuit includes a time-to-digital converter (TDC) having a reference clock input and an error input. A digital loop filter receives an output from the TDC representing a difference between the reference clock input and the error input. A digitally-controlled oscillator (DCO) receives an output from the digital filter in the form of output bits. The DCO has a codeword gain associated with a DCO control word. The codeword gain is applied to the output bits received from the digital loop filter. Calibration logic determines a scaling factor based on a process-voltage-temperature (PVT) operating characteristic. The scaling factor is applied to normalize an actual DCO codeword gain to the codeword gain. The DCO includes an output to deliver an output timing signal having a frequency based on the scaling factor.
    Type: Grant
    Filed: June 13, 2018
    Date of Patent: March 17, 2020
    Assignee: Movellus Circuits, Inc.
    Inventors: Frederick Christopher Candler, Jeffrey Fredenburg
  • Fast wakeup for crystal oscillator
    Patent number: 10594325
    Abstract: Techniques are described for fast wakeup of a crystal oscillator circuit. Embodiments operate in context of a crystal oscillator coupled with a phase-locked loop (PLL). For example, prior to entering sleep mode, embodiments retain a previously obtained coarse code used to coarse-tune a voltage controlled oscillator of the PLL. On wakeup, the PLL is configured in a chirp mode, in which the retained coarse code and a sweep voltage are used to generate a chirp signal at, or close to, a target stimulating frequency for the crystal oscillator. The chirp signal can be used to inject energy into the crystal oscillator, thereby causing the crystal oscillator to move from sleep mode to steady state oscillation relatively quickly.
    Type: Grant
    Filed: July 6, 2018
    Date of Patent: March 17, 2020
    Assignee: SHENZHEN GOODIX TECHNOLOGY CO., LTD.
    Inventors: Mohamed Aboudina, Ahmed Emira, Faisal Hussien
  • Digital phase locked loop clock synthesizer with image cancellation
    Patent number: 10594300
    Abstract: A frequency synthesizer includes a hardware digital controlled oscillator (HDCO) running at a first clock rate fS for generating an output clock signal in response to a control input, and a digital phase locked loop (DPLL) responsive to a reference input sampled at a second clock rate fsamp, the first clock rate fS being N times greater than the second clock rate fsamp, The DPLL includes a loop filter and a software digital controlled oscillator (SDCO). A first, first order linear interpolation anti-imaging filter running at a clock rate higher than said second clock rate fsamp is coupled to an output of the loop filter for providing the control input to the HDCO. A second, first order linear interpolation anti-imaging filter running at said second clock rate coupled to the output of said loop filter to provide an input to said SDCO.
    Type: Grant
    Filed: October 5, 2018
    Date of Patent: March 17, 2020
    Assignee: Microsemi Semiconductor ULC
    Inventor: Qu Gary Jin
  • Locked loop circuit with configurable second error input
    Patent number: 10587275
    Abstract: A locked loop circuit is disclosed. The locked loop circuit includes phase detection circuitry to generate a first error output based on a phase difference between a first reference input and a locked-loop output. Summing circuitry receives the first error output and a second error signal. The second error signal is based on one from a selection of error values. Oscillator/delay circuitry generates the locked-loop output. For a first mode of operation, the second error signal is based on a first selected error value. For a second mode of operation, the second error signal is based on a second selected error value different than the first selected error value.
    Type: Grant
    Filed: December 10, 2018
    Date of Patent: March 10, 2020
    Assignee: Movellus Circuits, Inc.
    Inventors: Jeffrey Fredenburg, Muhammad Faisal