Patents Examined by Joseph Chang
  • Patent number: 10574184
    Abstract: A stacked-die oscillator package includes an oscillator circuit die having inner bond pads, and outer bond pads, and a bulk acoustic wave (BAW) resonator die having a piezoelectric transducer with a first and second BAW bond pad on a same side coupled to a top and bottom electrode layer across a piezoelectric layer. A first metal bump is on the first BAW bond pad and a second metal bump is on the second BAW bond pad flip chip bonded to the inner bond pads of the oscillator circuit die. A polymer material is in a portion of a gap between the BAW and oscillator circuit die.
    Type: Grant
    Filed: May 1, 2018
    Date of Patent: February 25, 2020
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Ricky A Jackson, Kurt Peter Wachtler
  • Patent number: 10566983
    Abstract: An atomic oscillator includes: an atomic cell in which alkali metal atoms are sealed; a light source that radiates first light and second light with different frequencies to the atomic cell; a light detector that detects the first light and the second light transmitted through the atomic cell and outputs a detection signal according to a detection intensity; a signal generator that generates a microwave signal according to a transition frequency between two ground levels of the alkali metal atoms based on a result obtained by detecting the detection signal for each first period; and a light source adjuster that adjusts the frequencies of the first light and the second light for each second period, the second period being longer than the first period.
    Type: Grant
    Filed: August 24, 2017
    Date of Patent: February 18, 2020
    Assignee: Seiko Epson Corporation
    Inventors: Yoshiyuki Maki, Noriaki Tanaka
  • Patent number: 10566982
    Abstract: Embodiments described herein provide an electronic device, which includes a first oscillator configured to output a first clock signal, and a second oscillator that is co-located with the first oscillator on the electronic device. The electronic device further includes a first bandpass filter configured to filter a first input signal derived from the first clock signal received through a negative feedback loop, and to output a first signal component corresponding to the first signal spur. The electronic device further includes a signal reconstruction circuit configured to receive the first signal component and to combine the first signal component into a control signal for the first oscillator, and to feed the control signal combined with the first signal component to the first oscillator to mitigate the first signal spur exhibited in the first clock signal.
    Type: Grant
    Filed: November 14, 2017
    Date of Patent: February 18, 2020
    Assignee: Marvell International Ltd.
    Inventors: Luca Vercesi, Fernando De Bernardinis
  • Patent number: 10566956
    Abstract: An apparatus is provided comprising a first integrated circuit. The first integrated circuit comprises a first element comprising one of a transmit or receive element, an oscillator for providing a first local oscillator signal, a local oscillator output configured to output the first local oscillator signal when activated, a local oscillator input configured to receive a master local oscillator signal when activated; and first switching circuitry for selectively coupling the first element to one of the oscillator and the local oscillator input.
    Type: Grant
    Filed: December 15, 2017
    Date of Patent: February 18, 2020
    Assignee: NXP B.V.
    Inventor: Ralf Reuter
  • Patent number: 10566980
    Abstract: Disclosed is a method of locking a locked loop quickly, including receiving an input signal having an input frequency, and generating an intermediate signal having an intermediate frequency intended to be equal to a geometric mean of the input frequency and a desired frequency, but not equal. Results of division of the desired output frequency by the intermediate frequency are estimated, producing a first divider value. A first locked loop utilizing a controllable oscillator is activated. A divider value of the first locked loop is set to the first divider value, and the intermediate signal is provided to the first locked loop, so that when the first locked loop reaches lock, the controllable oscillator produces the desired frequency. When the first locked loop reaches lock, a second locked loop that utilizes the controllable oscillator is activated, the first locked loop is deactivated, and generation of the intermediate signal is ceased.
    Type: Grant
    Filed: March 19, 2018
    Date of Patent: February 18, 2020
    Assignee: STMicroelectronics International N.V.
    Inventors: Nitin Gupta, Jeet Narayan Tiwari
  • Patent number: 10559419
    Abstract: An inductor arrangement has a first inductor structure having one or more inductors at least partially on a first layer and a second inductor structure having one or more inductors at least partially on a second layer. The inductors are arranged such that currents induced by an external magnetic field are substantially cancelled in at least one of the first inductor structure and the second inductor structure. The, or each, inductor of the second inductor structure overlaps, at least partially, the, or each, inductor of the first inductor structure. An oscillator circuit having an inductor arrangement is also presented.
    Type: Grant
    Filed: May 18, 2018
    Date of Patent: February 11, 2020
    Assignee: Dialog Semiconductor B.V.
    Inventors: Thomas Dekker, Mark Oude Alink
  • Patent number: 10553775
    Abstract: According to one embodiment, an electronic circuit includes a first current path, a second current path, and a third current path. The first current path includes a first Josephson junction. The second current path includes a second Josephson junction. The third current path includes a plurality of third Josephson junctions. One end of the second current path is electrically connected to one end of the first current path. Another end of the second current path is electrically connected to another end of the first current path. One end of the third current path is electrically connected to the one end of the first current path and the one end of the second current path. Another end of the third current path is electrically connected to the other end of the first current path and the other end of the second current path.
    Type: Grant
    Filed: February 21, 2018
    Date of Patent: February 4, 2020
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Hayato Goto
  • Patent number: 10553462
    Abstract: Localized heating can be provided using fixed-frequency planar transmission line resonators arranged along a main-line, and tuning an electromagnetic input signal frequency applied to the main line to selectively address and energize one or more planar resonators for also addressing and energizing one or more correspondingly located active substrate transducer heat sources for depositing heat in an adjacent active substrate. More generally, adjusting input signal frequency to select one or more planar resonators arranged along a main line can be used to selectively address and energize an electromagnetic-to-heat, an electromagnetic-to-vibration, or other transducer to controllably direct energy toward a desired transducer load.
    Type: Grant
    Filed: July 3, 2019
    Date of Patent: February 4, 2020
    Inventor: Anand Deo
  • Patent number: 10554209
    Abstract: An apparatus is provided which comprises: a first ring oscillator comprising at least one aging tolerant circuitry; a second ring oscillator comprising a non-aging tolerant circuitry; a first counter coupled to the first ring oscillator, wherein the first counter is to count a frequency of the first ring oscillator; a second counter coupled to the second ring oscillator, wherein the second counter is to count a frequency of the second ring oscillator; and logic to compare the frequencies of the first and second ring oscillators, and to generate one or more controls to mitigate aging of one or more devices.
    Type: Grant
    Filed: March 22, 2018
    Date of Patent: February 4, 2020
    Assignee: Intel Corporation
    Inventor: Amit Kumar Srivastava
  • Patent number: 10549986
    Abstract: An illustrate method (and device) includes etching a cavity in a first substrate (e.g., a semiconductor wafer), forming a first metal layer on a first surface of the first substrate and in the cavity, and forming a second metal layer on a non-conductive structure (e.g., glass). The method also may include removing a portion of the second metal layer to form an iris to expose a portion of the non-conductive structure, forming a bond between the first metal layer and the second metal layer to thereby attach the non-conductive structure to the first substrate, sealing an interface between the non-conductive structure and the first substrate, and patterning an antenna on a surface of the non-conductive structure.
    Type: Grant
    Filed: September 7, 2017
    Date of Patent: February 4, 2020
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Juan Alejandro Herbsommer, Simon Joshua Jacobs, Benjamin Stassen Cook, Adam Joseph Fruehling
  • Patent number: 10541650
    Abstract: Systems and methods for interrogating sensing systems utilising bursts of samples. Bursts of samples correspond to optical pulses returning from optical sensors, where pulses are spaced at a period significantly longer than the pulse width, giving irregular sample spacing. The interrogation system and method processes the irregular busts of samples to recover phase information from received signals.
    Type: Grant
    Filed: February 5, 2016
    Date of Patent: January 21, 2020
    Assignee: Stingray Geophysical Hong Kong Limited
    Inventor: Julian Fells
  • Patent number: 10541695
    Abstract: A fast-locking phase locked loop and a fast locking method are provided. The fast locking method includes dividing a frequency of an oscillation signal by a preset divisor to output a divided signal, detecting a frequency difference between the divided signal and a reference signal, tracking whether a divided frequency of the divided signal falls within a locked frequency range or not, if not, tracking the divided frequency, and if yes, locking the divided frequency, detecting a divided phase difference between a divided phase of the divided signal and a reference phase of the reference signal, recording the phase difference as a tracking reference phase difference, tracking a next divided phase according to the tracking reference phase difference, and determining whether the divided phase falls within a locked phase range, and if not, tracking the divided phase, and if yes, locking the divided phase.
    Type: Grant
    Filed: September 6, 2018
    Date of Patent: January 21, 2020
    Assignee: ANPEC ELECTRONICS CORPORATION
    Inventors: Yuan-Hung Wang, Jing-Min Chen
  • Patent number: 10536152
    Abstract: An oscillating circuit has an injection-locked oscillator (ILO) and a calibration circuit. The ILO has a Gm cell and an LC tank. A first node of the Gm cell receives a first injection signal, and a second node of the Gm cell receives a second injection signal. The first injection signal and the second injection signal are differential signals. The Gm cell provides a negative resistance between a first output end and a second output end of the Gm cell. When the calibration circuit tunes a resonant frequency of the LC tank of the ILO, the magnitude of the negative resistance is reduced to control the ILO to stop self-oscillating. After finishing tuning the resonant frequency of the LC tank, the calibration circuit controls the ILO to start self-oscillating by increasing the magnitude of the negative resistance.
    Type: Grant
    Filed: October 21, 2018
    Date of Patent: January 14, 2020
    Assignee: KaiKuTek INC.
    Inventors: Pang-Ning Chen, Chen-Lun Lin, Ying-Chia Chen, Wei-Jyun Wang, Mike Chun Hung Wang
  • Patent number: 10536151
    Abstract: An injection locked oscillator (ILO) circuit is disclosed. The ILO circuit may include a first clock injection stage including a first programmable inverter in series with a first self-biased inverter. The first injection stage may receive a first input clock having a first frequency and generate a first injection signal. The ILO circuit may further include a second clock injection stage including a second programmable inverter in series with a second self-biased inverter. The second injection stage may receive a second input clock signal having the first frequency and to generate a second injection signal. The ILO may further include a phase locked loop (PLL) stage including a multi-stage ring oscillator. The PLL stage may receive the first injection signal and the second injection signal and to generate an output clock signal based at least in part on the first frequency.
    Type: Grant
    Filed: June 29, 2018
    Date of Patent: January 14, 2020
    Assignee: XILINX, INC.
    Inventors: Lei Zhou, Jinyung Namkoong, Stanley Y. Chen, Parag Upadhyaya
  • Patent number: 10535981
    Abstract: A device for preparing an ensemble of laser-cooled atoms and measuring their population includes a laser and a set of reflecting surfaces. The laser is able to produce a laser beam. The set of reflecting surfaces disposed to direct the laser beam along a multi-dimensional beam path to intersect a central space multiple times from different directions and retroreflect the laser beam to retrace the multi-dimensional beam path. The central space is able to have an ensemble of atoms or molecules. The atoms or the molecules are able to be cooled along one or more dimensions by the laser beam sent along the multi-dimensional beam path and able to be detected in the central space by an effect upon the laser beam sent along the multi-dimensional beam path.
    Type: Grant
    Filed: April 30, 2018
    Date of Patent: January 14, 2020
    Assignee: AOSense, Inc.
    Inventors: Martin M. Boyd, Adam T. Black, Brian R. Patton, Miao Zhu
  • Patent number: 10536112
    Abstract: An oscillator includes a container, a first heater disposed in a first area of the container, a second heater disposed in a second area of the container that is different from the first area, a vibrator disposed between the first area and the second area when viewed in the direction perpendicular to a surface on which the first heater is disposed, and a layer that is disposed between the vibrator and the container with at least part of the layer overlapping with the first heater, the second heater, and the vibrator when viewed in the direction perpendicular to the surface on which the first heater is disposed, and the thermal conductivity of the layer is higher than the thermal conductivity of the first and second areas.
    Type: Grant
    Filed: May 2, 2018
    Date of Patent: January 14, 2020
    Assignee: SEIKO EPSON CORPORATION
    Inventor: Manabu Kondo
  • Patent number: 10535980
    Abstract: An atomic oscillator device includes an atomic oscillator, a controlled oscillator, a resonance controller, and a cold-atom clock output. The atomic oscillator comprises a two-dimensional optical cooling region (2D OCR) for providing a source of atoms and a three-dimensional optical cooling region (3D OCR) for cooling and/or trapping the atoms emitted by the 2D OCR. The atomic oscillator comprises a microwave cavity surrounding the 3D OCR for exciting an atomic resonance. The controlled oscillator produces an output frequency. The resonance controller is for steering the output frequency of the controlled oscillator based on the output frequency and the atomic resonance as measured using an atomic resonance measurement. The cold-atom clock output is configured as being the output frequency of the controlled oscillator.
    Type: Grant
    Filed: April 30, 2018
    Date of Patent: January 14, 2020
    Assignee: AOSense, Inc.
    Inventors: Martin M. Boyd, Adam T. Black, Thang Q. Tran, Matthew D. Swallows, Brian R. Patton, Miao Zhu, Thomas H. Loftus, Mark A. Kasevich
  • Patent number: 10530297
    Abstract: A semiconductor device includes a reference voltage generation circuit configured to generate reference voltages Va and Vb capable of adjusting a primary temperature characteristic, and an oscillation circuit configured to output an oscillation signal using the reference voltages Va and Vb, in which the oscillation circuit includes a frequency/current conversion circuit that is driven by the reference voltage Va and outputs a current Ie in accordance with a frequency of a feedback signal, a control voltage generation circuit configured to generate a control voltage in accordance with a potential difference between a voltage in accordance with the current Ie and the reference voltage Vb, a voltage control oscillation circuit configured to output the oscillation signal having a frequency in accordance with the control voltage, and a frequency division circuit configured to divide a frequency of the oscillation signal and output the resulting signal as the feedback signal.
    Type: Grant
    Filed: March 22, 2018
    Date of Patent: January 7, 2020
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Guoqiang Zhang, Kosuke Yayama
  • Patent number: 10530298
    Abstract: According to one embodiment, there is provided a semiconductor device including a first switch, a first capacitive element, a second capacitive element, a first rectifying circuit, a second rectifying circuit, a third rectifying circuit, and a fourth rectifying circuit. The first switch is electrically inserted between a first node and a second node. The first capacitive element is electrically inserted between a first signal node and the first node. The second capacitive element is electrically inserted between a second signal node and the second node. The first rectifying circuit is electrically connected to the first node with a first polarity. The second rectifying circuit is electrically connected to the first node with a second polarity opposite to the first polarity. The third rectifying circuit is electrically connected to the second node with the first polarity. The fourth rectifying circuit is electrically connected to the second node with the second polarity.
    Type: Grant
    Filed: February 26, 2018
    Date of Patent: January 7, 2020
    Assignees: Kabushiki Kaisha Toshiba, Toshiba Electronic Devices & Storage Corporation
    Inventor: Hiroaki Hoshino
  • Patent number: 10518646
    Abstract: An electronic device including an electronic switch M1, an electrical pre-charge circuit and a measurement, command and diagnosis module. The main electronic switch M1 has a first electrical terminal D1, a second electrical terminal S1, and a main driving terminal G1. The main electronic switch M1 is adapted to take, based on a driving signal DRV, depending on the command signal CMD and on an enabling signal ENB, a closed condition or an open condition, wherein the first electrical terminal D1 is respectively connected to or disconnected from the second electrical terminal S1. The pre-charge electrical circuit is adapted to carry out, based on the command signal CMD, a pre-charge operation, aimed at equalizing the electric potentials (V1, V2) of the first and second terminals of the device, before the main electronic switch M1 takes a closed condition, upon of a transition from the open condition.
    Type: Grant
    Filed: May 18, 2018
    Date of Patent: December 31, 2019
    Assignee: MAGNETTI MARELLI S.p.A.
    Inventors: Danilo Pritelli, Franco Ciampolini, Rosanna Suglia, Gianluca Aurilio