Abstract: Each read line in a memory array containing a plurality of alternating bit lines and read lines with columns of memory cells therebetween, is broken into a plurality of electrically isolatable segments. As a result, the capacitance associated with each read line is significantly reduced and the speed of reading information from or writing information into a memory cell is significantly increased while at the same time not decreasing the density of the array.

Abstract: A semiconductor device includes a nonvolatile memory cell and a current detecting type sense amplifier for detecting a current flowing through a data line into the memory cell. The semiconductor device is further provided with an element for outputting a first voltage detecting signal when a detected supply voltage exceeds a set value and outputting a second voltage detecting signal when the detected supply voltage does not exceed the set value. The sense amplifier includes an element for switching a dependent characteristic of a level sensing current upon the supply voltage to be higher in response to the second voltage detecting signal that in response to the first voltage detecting signal. Thus, error reading of a data from the memory cell, which can be otherwise caused under application of a low supply voltage, can be avoided.

Abstract: A non-volatile memory device which enables use of a folded bit line system includes odd and even main bit lines, a plurality of sub-bit lines connected to the main bit lines through selection gates. Conductive and non-conductive states of the selection gate connecting to the odd main bit line and the selection gate connecting to the even main bit line are controlled by different selection signal lines so that the odd main bit line and the even bit line are operated selectively.

Abstract: A sensing circuit charges the bit lines of an associated memory array using one or more large-area pass transistors during reading operations of a selected memory cell of the memory array. In this manner, the read speed of the memory array is independent of the channel current of the memory cell. A sink transistor sinks a constant current from the selected bit line during reading to improve the noise margin of the sensing circuit so that memory arrays associated with the sensing circuit do not require the reference bit lines.

Abstract: An integrated memory circuit having an array of memory cells and which is operable in at least one test mode as well as in a normal operating mode, and a true V.sub.th measurement test implemented by such circuit The memory circuit includes circuitry for implementing a true V.sub.th measurement test mode in which an external voltage (or a sequence of external voltages) is applied to an external pad, and a test voltage at least substantially equal to such external voltage (or a sequence of test voltages, each at least substantially equal to one of a sequence of external voltages) is applied directly to the control gates of all or selected ones of rows of the cells (e.g., to all or selected ones of the wordlines of the array). In preferred embodiments, each memory cell is a nonvolatile memory cell such as a flash memory cell.

Abstract: A semiconductor memory device includes a memory cell array for storing data. The memory cell array includes a plurality of columns of memory cells and a plurality of bit lines connected to the memory cell array for reading out the data. The semiconductor memory device further includes a first precharge operation control circuit for performing a precharge operation with respect to all of the plurality of bit lines immediately after power is turned on.

Abstract: A redundancy circuit for a semiconductor memory device, comprising a first precharge transistor for transferring a precharge voltage to a first node in response to a first precharge signal, a second precharge transistor for transferring the precharge voltage transferred by the first precharge transistor to the first node in response to a second precharge signal, a first inverter for inverting a signal at the first node, an output terminal for transferring an output signal from the first inverter externally, a first NMOS transistor for transferring a supply voltage to the first node in response to a signal at the output terminal, a second inverter for inverting the second precharge signal, a second NMOS transistor for transferring a ground voltage to a second node in response to an output signal from the second inverter, a third NMOS transistor for transferring the ground voltage to the second node in response to the signal at the output terminal, a plurality of fourth NMOS transistors connected in parallel be

Abstract: A non-volatile semiconductor memory cell including: a plurality of blocks each having a plurality of floating gate transistors as memory cells, the floating gate transistor having a drain, a source, a floating gate, and a control gate capacitively coupled to the floating gate, and a data program of the floating gate transistor being effected by data write through injection of electrons into the floating gate and by data erase through emission of electrons from the floating gates; a circuit unit for applying an erase signal to a selected one of the blocks to emit electrons from the floating gates of a plurality of memory cells in the selected block and to erase data in all of the memory cells in the selected block at the same time; and a circuit unit for applying a write signal to the drains of the floating gate transistors within the selected block, without applying the write signal to the drains of the floating gate transistors of non-selected blocks.

Abstract: A flash-erasable semiconductor memory device comprises a memory cell array including a plurality of memory cell transistors each having an insulated floating gate for storing information and a control electrode provided on said floating gate, wherein the flash-erasable semiconductor memory device includes a write control circuit supplied with a write control signal, when writing information. The write control circuit produces a control signal such that a leading edge of the drain control signal appears after a leading edge of the gate control signal. Further, the gate control circuit shuts off the gate control signal such that a trailing edge of the gate control signal appears after a trailing edge of the drain control signal.

Abstract: Circuits and processes write and read analog signals in non-volatile memory cells such as EPROM and flash EPROM cells. One read circuit process determines a memory cell's threshold voltage by slowly ramps the control gate voltage of a memory cell being read and senses when the memory cell conducts. Another read circuit determines the threshold voltage of a memory cell using a source follower read process and a ramping circuit which slowly increases the source voltage. Still another read circuit includes a cascoding device connectable to a memory cell, bias circuit for biasing the memory cell in its linear region, and a load which carries a current that mirrors the current through the memory cell wherein the threshold voltage of the memory cell is determined from a voltage across the load. Read circuits disclosed can be used with analog memory cells, binary memory cells, multi-level digital memory cells, and other applications which require precise reading of threshold voltages.

Abstract: A cell array circuit for a programmable logic device is provided with split read and write lines in the memory cell. The circuit eliminates the need for pass gates in the speed path. The circuit includes steering logic, a row line driver circuit and a row decoder circuit to facilitate the different modes of operation of the cell array circuit.

Abstract: A non-volatile semiconductor memory includes a plurality of memory cells. Each memory cell includes N-type source and drain regions formed in a P-well on a semiconductor substrate, a floating gate formed on the P-well with a tunnel oxide film therebetween, and a control gate formed on the floating gate with an interpoly dielectric film therebetween. The memory has a plurality of bit lines, a plurality of word lines and a source line. The source region of each memory cell is connected to the source line. The drain region of each memory cell is connected to one of the word lines. The memory cell is written to, erased, or read by selectively supplying suitable voltages to the source, bit, and word lines connected thereto.

Abstract: A circuit for detecting timing errors and for selecting the correct clock edge for mid-point data sampling, includes a rising edge sampling device for sampling an input data signal at a rising edge of an input clock and generating a first interim data signal. A falling edge sampling device samples the input data signal at a falling edge of the input clock and generates a second interim data signal. An error signal generation devise, arranged in each of the rising edge and falling edge sampling devices, generates an error signal if designated setup time and hold time requirements are not met. The error signal is one of an error-rise or error-fall signal. A state machine receives the first and second interim signals and the error signal. The state machine automatically outputs the first interim data signal to a logic device if the error-fall signal is detected, and outputs the second interim data signal to the logic device if the error-rise signal is detected.

Abstract: A reference scheme for a Dynamic Shadow Random Access Memory which provides a reference voltage circuit used for determining the data state of a ferroelectric memory cell operating in either dynamic (DRAM) or nonvolatile (NVRAM) modes. The reference voltage circuit includes two ferroelectric capacitors with associated data state setting transistors such that in either DRAM or NVRAM operating mode, the two capacitors store opposite data states. The circuit also includes means for alternating the data state of each capacitor. In operation, the ferroelectric capacitors are discharged to associated bitlines producing voltages which are averaged to derive a half-state reference voltage level. The reference voltage is used to determine the state of an associated memory cell. Additionally, a ferroelectric memory circuit is provided which includes an array of reference voltage circuits configured and operated in a manner to reduce the fatigue and imprinting experienced by the reference capacitors.

Abstract: A semiconductor memory device includes a cell array having a plurality of memory cells grouped into a plurality of cell blocks and arranged in a matrix form, a plurality of word lines, a plurality of bit lines, bit line sense amplifiers (S/A), a cell block selection circuit, a plurality of data I/O lines, row decoders, a plurality of column selection signal lines, column decoders and a data buffer circuit.

Abstract: A ROM cell array in which the drains are more lightly doped than the sources. This reduces the worst-case capacitance seen by the bitlines, and consequently reduces the access time of the memory.

Abstract: The leakage current through a static random access memory ("SRAM") containing a plurality of memory cells connected between a voltage supply and a reference voltage, wherein each memory cell uses native transistors as load elements, is controlled by controlling the reference voltage.

Abstract: An integrated circuit includes primary circuit elements selectable by n address bits. A master storage device is programmable to indicate that at least one primary circuit element is being replaced. Redundant circuit elements each include a non-precharging matching circuit, which includes sub-match circuits. The sub-match circuits include two state storage devices corresponding to one of the possible binary values of at least one of the n address bits and activate a sub-match signal when the binary value of the at least one of the n address bits corresponds to one of the two state storage devices in a first state if the master storage device is programmed. A match circuit activates a match signal in response to all sub-match signals being active to disable a primary circuit element from being selected by a corresponding binary value of the n address bits and to enable the redundant circuit element to be selected by the corresponding binary value of the n address bits.

Abstract: First and second flash memory cells or transistors, operating in the linear region of operation, are provided with different threshold values by providing different charges on their respective floating gates. The first of the pair of flash memory transistors is "over-erased" until it has a negative threshold voltage so that the first flash memory transistor is rendered permanently conducting when its control gate and source are at V.sub.ss. Circuitry is provided for connecting the first and second flash memory transistors in parallel circuits in which equal current values are generated in an equilibrium condition. Circuitry for sensing a voltage in each of the parallel circuits is provided to determine any imbalance in current values and provide an output voltage which may be used as an reference value when the currents are in equilibrium.

Abstract: An integrated circuit package includes an integrated circuit device that operates in more than one operational mode. The operational mode of the integrated circuit device is controlled by a mode select input. Examples of operational modes include fast page and block modes, two- and three-latency modes, and normal and test modes. A reprogrammable mode select circuit within the integrated circuit package produces a mode control signal that drives a mode select input of the integrated circuit device. The operational mode of the integrated circuit device then corresponds to the state of the mode select signal.