Abstract: A memory cell array of high density, enabling high speed read-out. Diffusion wires columnwise extending in a block in the array serve as bit and ground lines alternately disposed and gate wires parallel to each other are formed perpendicularly to the diffusion wires. Channels are defined in regions between the adjacent diffusion wires under the gate wires, whereby MOS transistors are formed. A memory circuit has such a memory cell array and a decoder connected thereto. Paired adjacent bit lines are connected through a bit line select transistor to a contact, and the contact is connected through a metal line columnwise connecting between blocks, via a transistor of decoder to a main bit line. Paired adjacent ground lines are connected through a ground line select transistor to a contact for ground line, and the contact is connected through a metal line columnwise connecting between blocks, via a transistor of decoder to a main ground line.

Abstract: In a semiconductor memory device wherein a plurality of memory cell units formed by connecting a plurality of memory cells in series are provided and each of the memory cell units is connected to a bit line, the semiconductor memory device comprises control circuit for directly reading data of a register cell during a reading operation when the previous row address designates the same memory cell as the present row address, and a data changing controlling circuit for changing data of an arbitrary memory cell of the memory cell unit to data of the memory cell closest to the bit line contact in the memory cell unit, and a row decoder for corresponding row addresses which select the memory of memory cell units, to the upper addresses than the parts of the row addresses which select a memory unit among the memory cell units.

Abstract: Low power consuming circuitry for amplifying sensed signals in memory devices is disclosed. The low power circuitry includes a amplifier circuit having a data bus line for receiving a data signal from a selected column of a memory array. The data bus line being coupled to a first pre-charger transistor for limiting a data bus voltage swing, and a virtual ground control line for controlling a virtual ground application to a selected column of the memory array. The virtual ground application configured to provide a path to ground for the selected column, and the virtual ground control line being coupled to a second pre-charger transistor for limiting a virtual ground voltage swing. Further included is a gain transistor configured to receive the data signal from the data bus line and provide an amplified data signal to a pull down node located at an input of an inverter. And, a digital data output node located at an output of the inverter.

Abstract: The DRAM includes a plurality of main bit line pairs, a plurality of sense amplifiers, a plurality of word lines, a plurality of sub bit lines, a plurality of transfer gates, and a plurality of memory cells. The plurality of sub bit line pairs are arranged along each main bit line pair. The parasitic capacitance per unit length of a main bit line pair is at most 1/4 that of a sub bit line pair. Each transfer gate connects one main bit line and one sub bit line in response to a prescribed control signal. Thus, sufficiently large potential difference is generated between the main bit lines, and therefore the sense amplifier can surely amplify the potential difference.

Abstract: A plurality of static memory cells including CMOS flip-flops and switching MOS transistors are connected in series, thereby forming a memory cell unit in which one end of data reading is connected to bit lines. A series of the memory cell units are arranged, thereby forming a memory cell array. Reset terminals are provided for releasing cell data and causing the cell to function temporarily as a transfer gate of data.

Abstract: A driving circuit for a final decoding stage of an EPROM, EEPROM or FLASH EPROM for battery powered apparatuses functioning at relatively low supply voltage avoids energy absorption from a commonly boosted voltage node by switching the capacitance of the control node of the p-channel pull-up device of the CMOS inverter that drives the memory line and which constitutes the load of the driving circuit. The node is effectively charged by drawing current from the supply node and is discharged rapidly by switching in parallel thereto a previously discharged capacitance. This charge-sharing switcheable capacitance may advantageously be the capacitance of a similar p-channel pull-up control node of a deselected wordline of the array.

Abstract: A memory apparatus with dynamic memory cells that can be used both as a read-only memory and also as a volatile memory is provided. The memory apparatus has a capacitance value allocated to the capacitors present in the memory cells; the value is required for operation as a read-only memory. For read-only memory operation, memory cells are provided whose capacitors have different capacitance values corresponding to the type of information to be stored. A method of operating a memory apparatus is also provided. In the method, the information can be set by first charging all the memory cells and then applying a refresh signal to the memory cells with such a clock rate that the memory cells with the larger capacitance value do not discharge, but the memory cells with the smaller capacitance value discharge. In operation as a volatile memory, a refresh signal is applied to the memory cells in the standard way.

Abstract: A sense amplifier including a presense amplifier and a main sense amplifier. The presense amplifier detects a potential difference between a pair of bit lines based on information read from memory cells and outputs a pair of current signals in accordance with the detected potential difference. The main sense amplifier amplifies the pair of current signals from the presense amplifier to output a first pair of voltage signals. The main sense amplifier provides an output current which allows the first pair of current signals to flow through the presense amplifier. The main sense amplifier includes a current supply circuit for outputting a second pair of current signals based on the amount of the first pair of current signals output from the presense amplifier, and a converting circuit for converting the second pair of current signals from the current supply circuit to voltage signals and outputting the voltage signals.

Abstract: A circuit and method for reducing the leakage current drawn by a transistor when it is inactive. In a first implementation, a circuit selectively drives the gate of a transistor to a voltage level above a source voltage. As a result, the gate-source voltage is reversed and the leakage current flowing through the transistor is substantially reduced. In a second implementation, a circuit selectively biases the well of a transistor to a voltage level above a normal bias voltage. As a result, the voltage-current characteristics of the transistor are modified so that the leakage current is substantially eliminated.

Abstract: Disclosed is a defect relief decision circuit which has: a selection circuit for deciding either of a normal memory cell and a redundant memory cell to be used by cutting a fuse; a first programming fuse circuit which is controlled by the output of the selection circuit and to which an address bit of an address signal is input; a plurality of second programming fuse circuits which is controlled by the output of the selection circuit and to which an address bit different from the address bit of the address signal is input; and a logical circuit to which the outputs of the first and second programming fuse circuits are input and which decides to perform a defect relief operation when these coincide.

Abstract: Circuits and processes write and read analog signals in non-volatile memory cells such as EPROM and flash EPROM cells. One write process applies a control gate voltage which provides a saturation threshold voltage near a target threshold voltage being written. A verify feedback process terminates the write when the target threshold voltage is reached. Variable write pulse widths, voltages, and loadline resistances reduce write time and further improve control of writing. The fast write time of EPROM and flash EPROM cells simplifies control of write processes and therefore reduces chip size and cost in applications such as sound recording. A read process reads a memory cell's threshold voltage using substantially the same circuit as used in the verify feedback process. One read process determines a memory cell's threshold voltage by slowly ramping the control gate voltage and sensing when the cell conducts.

Abstract: An improved contactless EPROM array, EPROM cell design, and method for fabricating the same is based on a unique drain-source-drain configuration, in which a single source diffusion is shared by two columns of transistors. An elongated first drain diffusion region, an elongated source diffusion region, and an elongated second drain diffusion region, are formed in a semi-conductor substrate along essentially parallel lines. Field oxide regions are grown on opposite sides of the first and second drain diffusion regions. Floating gates and control gate wordlines are formed orthogonal to the drain-source-drain structure to establish two columns of storage cells having a shared source region. The shared source region is coupled through a bottom block select transistor to a virtual ground terminal. Each drain diffusion region is-coupled through a top block select transistor to global bitline.

Abstract: Circuits and processes write and read analog signals in non-volatile memory cells such as EPROM and flash EPROM cells. One write circuit to a control gate of a memory cell a voltage which after a long write time would saturate the threshold voltage of the memory cell near a target threshold voltage being written. One such write circuit includes a voltage shifter which generates the voltage to be applied to the control gate of the memory cell from an analog voltage representing a value to be written in the memory cell. A verify feedback circuit terminates the write when the target threshold voltage is reached. The write circuit uses variable write pulse widths, voltages, and loadline resistances to reduce write time and further improve control of writing. The fast write time of EPROM and flash EPROM cells simplifies control of write processes and therefore reduces chip size and cost in applications such as sound recording.

Abstract: Main bit lines MBL and ZMBL are disposed at opposite sides of a sense amplifier SA. Main bit lines MBL and ZMBL each are provided for paired sub-bit lines SBL1 and SBL2 (or SBL3 and SBL4). Sub-bit line pair SBL1 and SBL2 is connected to main bit line MBL via a block select switch T1. Sub-bit line pair SBL3 and SBL4 is connected to main bit line ZMBL via a block select switch T2. Since one main bit line is provided for two sub-bit lines, a pitch of the main bit lines is twice as large as a pitch of the sub-bit lines, so that conditions on the pitch of main bit lines are remarkably eased, which facilitates layout of elements.

Abstract: The present invention discloses a semiconductor integrated circuit device. This semiconductor integrated circuit has metal wiring layers of four levels including peripheral circuits of a memory module which are formed by word and bit lines in a lattice arrangement. The word lines are provided in the first-level metal wiring layer and the bit lines are provided in the second-level metal wiring layer. Provided in the third-level metal wiring layer is a first over-memory wire without direct access to any memory cell. A second over-memory wire without direct access to any memory cell is provided in the fourth-level metal wiring layer. The first and second over-memory wires for establishing connections between functional circuit blocks, are arranged in such a way that they extend across the word lines and the bit lines at an angle of 45 degrees.

Abstract: A processor (10) comprises a plurality of processing elements each having an input register (11), first memory bank (12), first sense amplifier (40), ALU (13), output register (16), second memory bank (15) and second sense amplifier (42). The first sense amplifier (40) is shared between the input register (11) and first memory bank (12). The second sense amplifier (42) is shared between the output register (16) and second memory bank (15). The sense amplifier (40,42) may be paused to prevent voltage spikes during a readrite operation, or to wait until a calculation is completed.

Abstract: A semiconductor memory comprises a write driver which is provided to correspond to respective data line and by which data lines connected with a memory cell through the control of a word line are driven in a write operation. The write driver includes MOSFETs of first group and MOSFETs of second group. In a case where a write enable signal does not designate the write operation, the MOSFETs of the first group are normally in ON states to pull up the data lines. Besides, in a case where the write enable signal designates the write operation, each of them operates in accordance with the value of input data, to maintain the ON states and pull up the corresponding data line in case of driving the data line to a "high" level and to fall into OFF states in case of driving the data line to a "low" level. On the other hand, the MOSFETs of the second group are normally in OFF states.

Abstract: A sense amplifier is provided which is appropriate for reading memory cells which control N-channel transistors, and which can read single ended registers. The sense amplifier pulls bit and bitbar lines to a high voltage before reading, and interprets equal voltages on two legs as a logical 1. Several embodiments are illustrated, one of which latches the value read from a memory cell, and one of which includes two stages.

Abstract: The present invention relates to a solid-state bi-stable circuit functioning as a six-bulk transistor static memory cell, the circuit comprising a plurality of bitlines and at least a first and second reference line, all of which are positioned in parallel with a plurality of wordlines. The circuit further comprises a plurality of transistors including a first and second load transistor, a first and a second pull-down transistor and a first and a second access transistor, in which each of the plurality of transistors includes a gate, source and drain. The gates of the plurality of transistors are positioned in parallel to minimize area usage.

Abstract: A clock feeding circuit to a semiconductor memory wherein the memory is comprised of separate independent control circuits each requiring a clock signal, comprising apparatus for receiving a control signal applied to one of the control circuits, and apparatus for applying a clock signal to the one of the independent control circuits, restricted to the one of the independent control circuits.