Abstract: A non-volatile semiconductor memory cell including: a plurality of blocks each having a plurality of floating gate transistors as memory cells, each floating gate transistor having a drain, a source, a floating gate, and a control gate capacitively coupled to the floating gate. The data program of the floating gate transistor is effected by data write through injection of electrons into the floating gate and by data erase through emission of electrons from the floating gates. A circuit unit applies an erase signal to a selected one of the blocks to emit electrons from the floating gates of a plurality of memory cells in the selected block and to erase data in all of the memory cells in the selected block at the same time. A circuit unit applies a write signal to the drains of the floating gate transistors within the selected block, without applying the write signal to the drains of the floating gate transistors of non-selected blocks.

Abstract: A programmable storage element for redundancy-programing includes a programmable antifuse circuit, which includes a plurality of first resistors and a switching circuit for coupling the first resistors in series in response to a plurality of first control signals and for coupling the first resistors in parallel in response to a plurality of second control signals to permit programing of the first resistors, and a sensing circuit for determining whether or not the first resistors have been programmed. The state of the first resistors is determined by comparing a first voltage drop across the first resistors with a second voltage drop across a second resistor. Each of the first resistors is an unsilicided polysilicon conductor which has an irreversible resistance decrease when a predetermined threshold current is applied for a minimum period of time.

Abstract: A dynamic random access memory device is equipped with sense amplifier circuits for developing differential voltage levels on associated bit line pairs, and the sense amplifier circuits are coupled through a discharging path with a ground voltage line, wherein the discharging path is implemented by a plurality of discharging sub-paths sequentially grounded by a control circuit so that the differential voltage levels are rapidly developed by smooth voltage decay on the associated discharging sub-paths, thereby improving the data access time.

Abstract: An electronic matrix array device such as a data store, e.g. a datacard, or an electro-optic active matrix display, has crossing sets of row and column conductors and matrix elements such as memory or picture cells at the crossing intersections. At least some of the matrix elements include a two-terminal thin film non-linear impedance element which may be bi-directional, such as a MIM, or unidirectional, such as a diode. The array device also includes a row address decoder for addressing the row conductors and a column address decoder for addressing the column conductors, either or both decoders having respective stages for respective conductors of the relevant set of conductors.

Abstract: Disclosed is an integrated circuit memory comprising at least one column of memory cells parallel connected with one another and connected to at least one bit line, each memory cell being connected to a bit line by at least one access transistor, wherein said memory contains a protection transistor that is connected to the bit line and controlled so as to be made conductive so as to limit the voltage drop on the bit line, during the stages of the reading of the memory, when this drop in voltage goes beyond a threshold having a value smaller than a value that prompts the writing of an information element in a memory cell.

Abstract: Provided is a semiconductor memory device wherein nonvolatile memory elements are arranged in a matrix configuration, each of the memory elements having a field effect transistor including a floating gate, an interlayer insulating film and a control gate electrode which are stacked on an insulating film covering a semiconductor substrate, and a source region and a drain region which are respectively formed in the semiconductor substrate on both sides of the gate electrode, the floating gate, interlayer insulating film and control gate electrode being formed in a recess provided in the semiconductor substrate. The semiconductor device of such a structure is reduced in size and highly integrated with its high-performance characteristics maintained.

Abstract: Sense amplifier performance is improved in a sense amplifier circuit connected to a semiconductor memory. A current mirror circuit is connected to a data node on the side of a pass transistor adjacent to core memory. The other side of the current mirror circuit is connected to modify the current provided from a memory reference cell. This provides a lubricating current to the pass transistor to ensure that it does not shut down in the absence of current flow from a core memory cell. Sense amplifier speed is improved by a higher transconductance level in the pass transistors. Speed is improved by reducing sense node capacitance through buffer circuitry. Core performance is enhanced by interspersed reference columns within the core at distributed locations.

Abstract: In a memory card according to the present invention, a full CMOS type volatile memory element is employed as a memory for storing attribute data. The full CMOS type volatile memory element has a low data holding voltage, consumes less power, has a short data writing time, and is less expensive than a programmable non-volatile memory element. Further, an internal power source line is provided for the volatile memory element separately from an internal power source line for a volatile memory element for storing data, and a capacitor having a large capacity or a secondary cell is connected to the internal power source line to further increase the data holding time. The volatile memory element for storing attribute data may be combined with a control circuit. Consequently, the production cost of the memory card for storing attribute data and the attribute data writing time can be reduced.

Abstract: A ROM device provides a double density memory array. The word line array is composed of transversely disposed conductors sandwiched between two arrays of bit lines which are orthogonally disposed relative to the word line array. The two arrays of bit lines are stacked with one above and with one below the word line array. A first gate oxide layer is located between the word line array and a first one of the array of bit lines and a second gate oxide layer is located between the word line array and a the other of the arrays of bit lines. The two parallel sets of polysilicon thin, film transistors are formed with the word lines serving as gates for the transistors.

Abstract: A nonvolatile semiconductor memory device includes rewritable areas (M10, M20). A control circuit (110) controls a boosting circuit (2) and a writing circuit (10) such that a high voltage is generated from the boosting circuit, and data is written to the rewritable area designated by an address register/decoder (104) by means of the writing circuit. In response to an external signal which is at the "H" level, the control circuit allows writing of data to the rewritable areas (M10, M20) by means of the writing circuit (9). In response to an external signal which is at the "L" level, the control circuit prohibits rewriting of data in the rewritable area (M10), and allows rewriting of data in the rewritable area (M20). Therefore, even if the operation mode is erroneously set to the write mode because of unstable state of the power supply, data in the rewritable area is not destroyed.

Abstract: A semiconductor integrated circuit comprises a semiconductor chip, a power supply terminal provided on the semiconductor chip for receiving a voltage from an external power supply source, an internal circuit provided on the semiconductor chip, a power supply circuit provided on the semiconductor chip for transforming an external power supply voltage received from the power supply terminal for supplying a source voltage resulting from the voltage transformation to the internal circuit, and a control circuit provided on the semiconductor chip for controlling the power supply circuit, wherein the control circuit includes external power supply voltage detecting means and/or temperature detecting means and responds to the signal from the external power supply voltage detecting means and/or the temperature detecting means by changing the power supply voltage to the internal circuit to thereby maintain the operating speed of the internal circuit to be constant.

Abstract: The semiconductor memory device according to this invention includes a memory cell array which comprises plural memory cells arranged in row and column direction in the form of an array, plural bit line pairs for connecting these memory cells in the unit of a column and word lines for connecting these memory cells in the unit of a row, sense amplifiers which are respectively connected to each of the bit line pairs at one end thereof and which amplify the potential difference between the bit lines of each pair in response to activation signals, and transfer gate means which divide said plural bit lines respectively into at least two portions corresponding to control signals, the sense amplifiers for the bit line pairs which belong to the nth columns (n is an odd numbered integer) thereof being arranged on one end of the bit line pairs and on the other end thereof for the those which belong to the (n+1)th columns.

Abstract: Disclosed is a semiconductor integrated circuit wherein a logic circuit for exchanging signals with RAMS, with the RAMS being disposed centrally on the semiconductor chip or substrate, is divided into a plurality of logic circuits in accordance with the kind of signals and the divided logic circuits are disposed around the RAM in such a manner as to minimize the distance of signal transmission paths with the RAM and in order to attain high speed access to RAMS.

Abstract: A novel row decoder/driver circuit in which switched bias voltages are applied to the bulk regions in order to minimize the maximum voltage differential appearing across transistor devices. This allows the decoder/driver circuit to be conveniently fabricated and designed to allow normal transistors rather than more complex and expensive high voltage transistors, to form the row decoder/driver. The bulk regions containing the pull-up and pull-down transistors are biased by voltages which are switched during erasure depending on whether the row line is selected or deselected in order to assure that excessive voltages do not appear across based upon the voltage levels applied to the transistors.

Abstract: A method for manufacture of a full CMOS type SRAM, comprising the steps of forming a first mask layer on a semiconductor layer, and patterning the first mask layer by photolithography to form semiconductor island layers where a driver MOS transistor and a load MOS transistor are formable with a slight space therebetween; forming a second mask layer on the semiconductor layer, and patterning the second mask layer by photolithography in such a manner as to overlap the region with one of the driver and load MOS transistors, but not to overlap the isolating region between the transistors; masking, with a resist film, the region with the other of the driver and load MOS transistors, and etching the first mask layer while masking the same with the resist film and the second mask layer; and etching the semiconductor layer while masking the same with the first mask layer, thereby forming mutually isolated semiconductor island layers where the driver and load MOS transistors are formed respectively.

Abstract: A CMOS memory is disclosed which employs a column selector circuit that prevents write disturb in shared column EPROMs. When a selected memory transistor is programmed, disturb is prevented by selecting all columns on the source side of the selected memory transistor to be tied to the source programming voltage, and selecting all columns on the drain side of the selected memory transistor to be tied to the drain programming voltage. By reducing voltage differentials across non-selected memory transistors, write disturb is prevented. This may be implemented by employing shorting devices between all adjacent columns. When a memory transistor is selected, all the shorting devices except the one between the source and drain columns of the selected memory cell are enabled. This may be further improved to minimize the number of required select lines by employing a shorting device comprising transistors controlled by the normal select lines.

Abstract: An improved over-erased bit correction structure is provided for performing a correction operation on over-erased memory cells in an array of flash EEPROM memory cells after erase operation so as to render high endurance. Sensing circuitry (20) is used to detect column leakage current indicative of an over-erased bit during an APDE mode of operation and for generating a logic signal representative of data stored in the memory cell. A data input buffer circuit (26) is used to compare the logic signal and a data signal representative of data programmed in the memory cell so as to generate a bit match signal. A pulse counter (30) is coupled to the data input buffer circuit for counting a plurality of programming pulses applied thereto.

Abstract: A semiconductor memory device comprises read-out circuits responsive to first column address decoded signals for transferring data bits from selected bit lines to data line pairs, selector circuits responsive to second column address decoded signals for transferring a data bit from selected one of the data line pairs to a read data amplifier circuit and a precharge circuit coupled between a source of power voltage level and the data line pairs for charging the selected data line pair before transmission of the data bit to the selected data line pair, and the precharge circuit isolates the data line pair from the source of power voltage level so that potential difference indicative of the data bit rapidly takes place on the selected data line pair.

Abstract: A memory cell circuit for a CMOS static RAM is provided, which includes a latch portion for holding logic high or logic low data depending on the potential of a single bit line, and a transfer gate having a first terminal connected to the latch portion and a second terminal connected to the single bit line, the transfer gate electrically connecting or disconnecting the first and second terminals in response to a selection signal, wherein the transfer gate includes a first transistor and a second transistor connected in parallel between the first and second terminals, both of the first and second transistors being activated at a data write operation, while one of the first and second transistors being activated at a data read operation.

Abstract: The invention relates to a memory element in current circuit technology having a first, a second and a third transistor pair each with emitter coupled transistors. Each of the second and third transistor pairs is connected in the collector circuit of a respective one of the transistors of the first transistor pair. Connected in each of the pairwise coupled collector circuits of the transistors of the second and third transistor pairs are a first resistor, the collector-to-emitter path of a further transistor with an output signal terminal disposed on the collector side and a second resistor. The collector of one transistor of a fourth transistor pair connected as a current switch is connected with the base of one of the further transistors. The setting and resetting of the memory element is made possible by the fourth transistor pair without increasing the capacitive load on the signal path of the memory element.