Abstract: In a memory card designed to count down a number of units by successive programming of non-volatile, electrically erasable and electrically programmable memory cells, the memory is organized into N rows of P cells, the weight of the cells of one row in the account being P times the weight of the next-ranking row. The countdown procedure is recurrent and consists in making a search, in scanning the memory according to the rising order of weights, of an erased cell, programming this cell and an erased cell and then erasing the entire row having an immediately lower rank unless the erased cell is located in the first row, and in recommencing this recurrent procedure until an erased cell is found in the first line. The auxiliary cell enables the detection of an abnormal interruption of the recurrent procedure and the restoring of the exact account of the memory which could have been distorted by this abnormal interruption.

Abstract: A semiconductor device having a programmable memory cell which includes a bipolar transistor of which a base region (13) can be provided with a base current through a control transistor (7, 8, 9, 10). The bipolar transistor has an emitter region (12) connected to a first supply line (151) and has a collector region (14) connected to a second supply line (152) through a load (16). A constant potential difference is maintained between the two supply lines (151, 152) during operation. The collector region (14) is laterally electrically insulated and provides a feedback to the control transistor in such a manner that, during operation within a certain voltage domain, a change in the voltage difference between the emitter region (12) and the collector region (14) leads to an opposite change in the conductivity through the control transistor.

Abstract: A semiconductor memory includes a memory cell for storing data; a bit-line pair to be charged to an electric potential corresponding to the data stored in the memory cell; a data-line pair to be electrically connected to the bit-line pair; and a main amplifier for amplifying an electric potential difference of the data-line pair and outputting a signal corresponding to the data. The main amplifier restrains itself from outputting the signal corresponding to the data until the electric potential difference of the data-line pair becomes higher than a predetermined value.

Abstract: This invention relates generally to the accessing of random access access memory arrays and, more specifically to circuits and techniques for increasing the data valid time of such memory arrays without increasing either the access or cycle times of the array. This is accomplished by providing, during a read cycle, a read signal directly to an output driver and simultaneously providing, via a parallel path, a latch output to the same driver. The latch output is provided under control of the read signal and a returning portion of a clock pulse such that the latch output overlaps the direct read signal from a read/write amplifier. An output is provided from the latch until it is reset and may last well into the next read cycle even when a new read signal is present.

Abstract: A three-dimensional memory cell, suitable for electrically erasable programmable read only memories (EEPROMS), which has direct-write cell capability is disclosed. The memory cell is utilized in the fabrication of non-volatile, direct-write EEPROM arrays with high integration density. A typical EEPROM array includes a plurality of elongated shallow trenches formed in a semiconductor substrate. Multiple direct-write EEPROM cells are disposed within each elongated trench such that each EEPROM cell shares a recall gate and a program gate with another cell in the same trench. Preferably, a silicon rich dielectric (such as silicon rich oxide) disposed between each floating gate and its associated programming and recall gates. Both common source diffusion and isolated source diffusion embodiments are disclosed. Further, various fabrication methods for the direct-write EEPROM arrays presented are described.

Abstract: A read/write/restore circuit is disclosed for use in a memory array such as a static RAM array. The circuit employs data and data-complement signals having three states in combination with a two-state address signal to perform read, write and restore functions for the array, to reduce the number of components and control lines needed. The circuit is preferably implemented in BICMOS technology.

Abstract: A semiconductor memory device of folded bit line structure provided with a cross portion in at least one portion of each of bit line pairs so that values of coupling capacitance with adjacent bit line pairs are equal to each other with respect to the paired bit lines.Preferably, the respective bit line pairs are equally divided into 4N and the cross parts are provided at dividing points so that bit line pairs having the cross parts at the same dividing points are arranged on alternate pairs of bit lines.Preferably, the cross parts are provided in regions for forming restore circuits or sense amplifiers.More preferably, a dummy word line for selecting dummy cells for providing reference potential is selected by the position of a selected word line.

Abstract: A flash electrically erasable programmable read only memory (EEPROM) device includes a two-dimensional array of single transistor non-volatile memory cells having the mid channel injection mechanism. The single transistor non-volatile memory cell includes a select gate, a control gate, and a floating gate which are disposed above a channel between a source and a drain. The control gate is located above the floating gate. In order to program the memory cell, the carrier injection into the floating gate is accomplished by the deflection of accelerated carriers from the middle region of the channel. Carriers are accelerated through the carrier acceleration passage by the horizontal component of the stray electric field, and deflected by the vertical component of the electric field. The erasure of memory cell is accomplished by the tunneling of carriers from the floating gate to the drain.

Abstract: An integrated circuit which provides an arrangement by which the source of voltage for erasing the flash EEPROM memory array is detected and, if the source is a charge pump, the current provided is held to a constant lower value while, if the source is an external high voltage source, then the current is allowed to flow freely without regulation except by the size of a field effect transistor device in the path from the source of voltage to the memory array. In this manner, the circuitry is adapted to function with either internal or external power sources without paying a performance penalty for either type of operation.

Abstract: A shift register comprises a plurality of amorphous silicon thin-film transistors configured in a plurality of register cells through which data is shifted through a plurality of amorphous silicon thin-film floating-gate transistors. In the event power is cutoff or lost, the floating gate transistors non-volatilely store the data which can be recovered or restored when power is subsequently turned on. Each cell comprises two stages in which data signals are written before being input into the next stage and next cell. A clock generator receives clocking signals for controlling the shifting of data through the register.

Abstract: In a static type semiconductor memory device having a memory cell, the memory cell includes a flip-flop which has first and second nodes, a first transfer gate transistor which is connected between a first bit line of a pair of complementary bit lines and the first node, a second transfer gate transistor which is connected between a second bit line of the pair of complementary bit lines and the second node, a first capacitor which is connected between a word line and the gate of the first transfer gate, and a second capacitor which is connected between the word line and the gate of the second transfer gate. By the structure, even if the cell ratio is made small, it is possible to achieve stable operation at a low operating voltage and possible, thereby, to achieve both low power consumption and a high degree of integration.

Abstract: A portion of a cell plate 91 extending upon a field oxide film 107a and a silicon oxide film 123 is referred to as a lower layer interconnection film 109. The lower layer interconnection film 109 has a concave shape. A through hole 95a is formed in a silicon oxide film 93 reaching the bottom of the concave shape lower layer interconnection film 109. The depth of the through hole 95a is greater in comparison with the case where a through hole is formed on an upper face portion 123a of the silicon oxide film 123. Because the depth of through hole 95a is great, the thickness of the tungsten film 101a formed in through hole 95a becomes thicker. This eliminates the problem that all the tungsten film 101a in the through hole 95a, and then a portion of the lower layer interconnection film 109 are overetched. Therefore, electrical connection between the upper layer interconnection layer 103a and the lower layer interconnection layer 109 can be ensured.

Abstract: An elastic store memory circuit includes first and second elastic store memories. Each of the first and second elastic store memories generates a phase comparison signal when a phase difference between a write timing and a read timing is within a predetermined phase range. The elastic store memory circuit also includes a selector which selects either the input data read out from the first elastic store memory or the input data read out from the second elastic store memory, and a slip signal generator for generating a slip signal on the basis of a write reset timing at which the first and second elastic store memories are reset, a read reset timing at which the first and second elastic store memories are reset, and the phase comparison signal. The slip signal indicates which one of the write reset timing and the read reset timing precedes the other one.

Abstract: An integrated circuit which provides an arrangement by which the source of voltage for erasing the flash EEPROM memory array is detected and, if the source is a charge pump, the current provided is held to a constant lower value while, if the source is an external high voltage source, then the current is allowed to flow freely without regulation except by the size of a field effect transistor device in the path from the source of voltage to the memory array. In this manner, the circuitry is adapted to function with either internal or external power sources without paying a performance penalty for either type of operation.

Abstract: A semiconductor memory device includes an address input circuit for receiving an address signal and outputting an internal address signal corresponding to the received address signal; an address decoder for decoding the internal address signal and outputting a decoded signal; a memory cell array having a plurality of memory cells each capable of storing data, as selected by the decoded signal, the selected memory cell outputting memory cell data; and an output circuit for outputting a truth data and false data at the same time in accordance with the output memory cell data of the selected memory cell.

Abstract: A mask ROM having a defect repairing function stores address signals corresponding to a defective memory cell and then, selectively activates either a redundancy row decoder or a row decoder according to whether the address signals stored are identical to address signals supplied externally. The mask ROM includes first and second memory cell arrays formed by grouping in a word line direction a plurality of read only memory cells arranged in rows and columns; first and second row decoders for combining row address signals supplied externally so as to selectively drive the word lines of the first and second memory cell arrays; and a row decoder selector for storing therein address signals according to a row block including a defective memory cell, of the first memory cell array so as to inactivate the first row decoder and activate the second row decoder when the external row address signals are equal to the address signals stored in the row decoder selector.

Abstract: A static RAM includes test features which provide for the detection of soft defects which may cause a defective SRAM cell to behave as a functional DRAM cell. Provision is made for writing either a high or a low logic state to each bit line of the SRAM while not writing any value to its complementary bit line and for sensing the state of each bit line independently of the state of its complementary bit line. In addition, a current test is provided which detects soft defects by means of the increased inverter leakage current caused thereby. It is possible, by properly combining these tests, to reliably detect all soft defects, thereby assuring the data retention capability of the SRAM. This technique avoids the long hold time and/or high temperature test techniques used in the prior art.

Abstract: A method of this invention is applied to a nonvolatile memory device composed of first memory cells connected to one of a first word-line pair and second memory cells connected to the other of the first word-line pair, and a single source shared by the first memory cells and the second memory cells. First, a positive potential of, for example, 5 V is applied to the source, a negative potential of, for example, -10 V is applied to the one of the word-line pair, and the ground potential to the other of the word-line pair. This permits electrons to move from the floating gate of the first memory cells into the source, with the result that the erasing of information is achieved. Next, the positive potential is applied to the source, the negative potential is applied to the other of the word-line pair, and the ground potential to the one of the word-line pair.

Abstract: A nonvolatile semiconductor memory, which includes an array of programmable transistor cells, such as EPROM or EEPROM cells, provides electrical isolation without the use of field oxide islands. The cells are arranged in X number of rows and Y number of columns with the cells in at least two of the rows being designated as select cells and the remaining cells being designated as memory cells. Control circuitry is provided for causing the select cells to supply programming voltages to selected ones of the memory cells. Alternate ones of the select cells are formed as implanted-channel select cells to provide electrical isolation for adjacent select cells which remain in the low threshold (active) state. The implanted-channel select cells are formed by implanting a material into the channel region of each of the implanted-channel select cells to increase the threshold voltage of the cells, thereby preventing the implanted channel select cells from conducting when normal operational voltages are applied.

Abstract: According to this invention, a semiconductor apparatus includes a word line group consisting of four word lines, a bit line pair group, word line drive circuits, arrangement patterns of which are alternately inverted, for outputting boosted word line signals to the word line group, and memory contact portions provided to the bit line pair group in a 1/4-pitch system, wherein output terminals of the word line drive circuit having an inverted arrangement pattern are connected to memory cells so as to be aligned in the same order as in output terminals of the word line drive circuit having a non-inverted arrangement pattern.