Abstract: A manufacturing process for establishing optimal operating limits, which are a percentage of a specified or blue-print tolerance, for the critical characteristics of manufactured products. The process begins a selection step for establishing an operating range based upon a percentage of tolerance for the critical characteristics of the manufactured product. The next step of the process is the manufacturing step including; making a determination as to whether the manufacturing apparatus is capable of operating within the proposed operating range, evaluating the fitness of the materials, manufacturing the products within the proposed operating range, and measuring the critical characteristics of the manufactured products. The process is audited to verify that product critical characteristics are maintained within the operating range. Any products whose critical characteristics are not within the operating range is rejected and is not offered for sale to customers in the relevant market.

Abstract: A reconfigurable processor includes at least three (3) MacroSequencers (10)-(16) which are configured in an array. Each of the MacroSequencers is operable to receive on a separate one of four buses (18) an input from the other three MacroSequencers and from itself in a feedback manner. In addition, a control bus (20) is operable to provide control signals to all of the MacroSequencers for the purpose of controlling the instruction sequence associated therewith and also for inputting instructions thereto. Each of the MacroSequencers includes a plurality of executable units having inputs and outputs and each for providing an associated execution algorithm. The outputs of the execution units are input to an output selector which selects the outputs for outputs on at least one external output and on at least one feedback path. An input selector (66) is provided having an input for receiving at least one external output and at least the feedback path.

Abstract: An object code expansion program inserts new instructions and data between preexisting instructions and data of an object code file; offsets are modified to reflect new positions of the preexisting instructions and data. For each item of preexisting object code (instructions or data), the following steps are performed: making a new code block comprising any desired new instructions and the item, and storing it as new object code; tracking the location of the item and the new code block within the new object code; and tracking items that contain inter-item offsets. Then, each inter-item offset is updated using the new location of the item or new code block, as required. Finally, offsets in symbol tables and relocation structures are updated with the new location of the item. This expansion program is used to add instructions to object code files of a second program, to monitor substantially all of the memory accesses of the second program.

Abstract: Inventory maintenance is improved for a system of one or more vending machines by providing one or more vending machines with unique identifiers, and means for collecting and transmitting information concerning goods dispensed and other status to a remote location where processing means provide an efficient service schedule.

Abstract: A fault-tolerant code semiconductor memory storage device includes a array of individual multi-level storage devices arranged in a prescribed sequence. A controller is provided for programming the array with sequential data. The controller detects an occurrence of a faulty storage device in the array during a programming of the array with the sequential data. The controller further codes the occurrence of the faulty storage device in a subsequent storage device in the sequence of devices using a fault-tolerant code. A method of fault-tolerant coding of a semiconductor memory storage device is also disclosed.

Abstract: A computer recovery system provided on a removable high capacity disk. In the event that a user encounters an abnormal operating condition, the user inserts the removable high capacity disk into the computer and restarts the computer. The computer boots either directly from the removable high capacity disk or from a floppy disk which transfers control to the removable high capacity disk. The removable high capacity disk includes all of the files necessary to load the computer operating system and launch the graphical user interface of the operating system such that the user is provided with a familiar operating environment. The removable high capacity disk also includes a suite of software recovery software which attempt to ascertain and correct the cause of the abnormal operating condition to return the computer system to a normal operating condition.

Abstract: A method of automatically configuring and formatting a computer system for installation of a prespecified application program in the computer system, which includes the performing the following acts: automatically creating a primary active DOS partition on a primary hard disk drive of the computer system; automatically selecting a size value for a primary extended DOS partition; automatically creating the primary extended DOS partition on the primary hard disk drive, wherein the size of the primary extended DOS partition equals the selected size value; automatically formatting each partition so as to create a root directory and a file allocation table for each partition; and automatically executing a DOS batch file in order to install said prespecified application program.

Abstract: A CPU plug-and-play method includes driving the I/O chip of a computer to generate two reset signals when the computer is booted to respectively reset the ISA and PCI buses of the computer main board, at the same time issuing a CPU control signal to a system logic chip of the computer to gain control of the CPU working frequency setting operation, and transmitting a selected working frequency set by the user via system firmware to a multiple frequency factor control circuit through a universal bus. The multiple frequency control circuit generates and transmits a multiple frequency factor to the CPU by applying a reset signal to the system chip set in response to the multiple frequency factor to generate a CPU reset signal which instructs the CPU to adapt the working speed in accordance with the new multiple frequency factor so that no jumper or other switch is needed to be manipulated in changing working frequency. Thus a plug-and-play method for CPU is provided.

Abstract: In a debugging system for use in realizing simultaneously complete observation of internal operation and reproduction of malfunction actually caused in a target system which includes an integrated circuit, such as a microprocessor, contents of a memory and an internal initial state of the target system are snooped and stored in a snoop unit and a trace memory, respectively, both of which are included in a probe unit attached to the target system. The internal operation and the reproduction are simulated by a software simulator model by the use of the contents and the internal initial state which are stored in the trace memory and which are sent from the probe unit.

Abstract: A system for a network gateway that provides computer data security using a protocol stack proxy is disclosed. The system evaluates data that arrives at a computer system that is executing a network operating system. The system comprises a protocol stack proxy, coupled between a device driver on the computer system that is configured to receive the data from a network and deliver the data according to a first protocol associated with a first network layer, and one or more components of the network operating system that receive packets according to the first protocol.

Abstract: A tool control for operating a tool in a mulitple station foam injection station including a central controller which is configured to use a first set of inquiry signals and a first set of control signals to monitor and control a standard tool, the tool control being configurable for interfacing with the central control and operating a nonstandard tool.

Abstract: A compact hardware key for protecting software executing on a computer is disclosed. The hardware key uses a two piece insulator design in which each insulator piece provides a double layer insulator body for protection from tampering, insulator areas for electrically isolating I/O connector pins, and an integral circuit board support portion for securely mounting the circuit board assembly. The compact hardware key also comprises a unique coaxially displaced interrupt pin structure.

Abstract: An .times.86 based computer system that implements a firmware based boot process without an .times.86 BIOS that supports expansion devices coupled to the computer system, wherein the expansion devices include their own respective BIOS extensions. The computer system includes an .times.86 processor coupled to a volatile memory and a non-volatile memory via a bus. The non-volatile memory includes firmware which when executed by the processor cause the computer system to implement the boot process. The firmware initializes device drivers for the computer system and initializes an application programming interface for the device drivers. The firmware then initializes a compatibility component for interfacing with the device drivers, wherein the compatibility component is operable for translating accesses by a first software application to an .times.86 BIOS into corresponding accesses to the device drivers.

Abstract: A method and system for enabling/disabling automatic encryption engines/algorithms using the Global Positioning System for country/locale verification and compliance with federal encryption export statutes.

Abstract: A computer system and new method of generating peripheral device configurations in a computer system having multiple types of system resources is disclosed. The method defines a resource priority list for the system resources and configures a device a resource type at a time based on the resource type priority list. The resource priority list is a function of the number of resource items for each system resource and the available resources in the computer system. The method thus serves to minimize the number of testing or checking iterations in configuring a device, whereby significant improving device configuring and conflict resolution in a computer system.

Abstract: An apparatus includes a storage medium having stored therein a segmented basic input/output system (BIOS) divided among a plurality of segments within the storage medium, and a processor operative to execute the segmented BIOS. In accordance with the teachings of the present invention, the BIOS includes a recovery function that is mode dependent in that while the apparatus is in an update mode the recovery function executes a full reflash of all relevant segments of the segmented BIOS, whereas while the apparatus is in a normal mode the recovery function executes a partial reflash of only identified corrupted BIOS segments.

Abstract: A computer system utilizing the Advance Configuration and Power Interface (ACPI) Standard to notify an ACPI compliant operating system of a detected correctable error. The computer system includes and error check circuit that detects correctable and non correctable errors in computer information flowing between the processor and a RAM. The error correction circuit provides a CE signal in response to detecting a correctable error. The computer system includes a register block circuit, that when enabled, generates an SCI to the processor in response to receiving the SCI. The processor accesses a status register of the SCI to determine that the error signal was sent. An ACPI driver of the operating system interprets ACPI control methods to direct the processor to perform the functions of the control method to obtain an address and syndrome of the information unit having the detected correctable error.

Abstract: The present invention provides a new memory device for storage of boot code for microprocessors which boot to either the top or bottom of a memory map on power-up. The device includes a memory array, a first block, and decoders. The first block is defined as rows of the memory array designated for storage of data. The decoders decode a memory access requested for the data. The memory access request may be in either one of a top-down or bottom-up address protocol. In another embodiment, an integrated circuit memory includes: a memory array, a decoder, a control, and a logic gate. The decoders decode a memory access request to select a row of memory array. The control has an output for outputting either a bottom-up or a top-down address protocol signal. The logic gate outputs a logical "Exclusive Or" of the control signal and a corresponding bit of the memory access request, whereby a memory request in a bottom-up address protocol is converted to a memory address in a top-down address protocol.

Abstract: A method and device which powerswitches a display monitor through the reset of a microcomputer is adapted to interrupt the latch up caused during the use of a soft power key by reading the power state of the display monitor before latch up from a memory, and switching the power state to the state before the latch up of the display monitor.

Abstract: A system for timing intervals in a computer. The system provides an interval timing service for processes running in a computer system. The timing service supports a potentially large number of interval timers by using "timing wheels" that "turn" at different periods. The time base for the fastest turning wheel can be an interrupt event or some other hardware or software control.