Abstract: A system for timing intervals in a computer. The system provides an interval timing service for processes running in a computer system. The timing service supports a potentially large number of interval timers by using "timing wheels" that "turn" at different periods. The time base for the fastest turning wheel can be an interrupt event or some other hardware or software control.

Abstract: An access control processor provides for display of a message related to an authorization status of an information receiver in a conditional access system for receiving an information segment when the information segment is provided separately by each of a plurality of different service providers. The processor processes a plurality of authorization signals respectively related to the information segment provided separately by the plurality of different service providers; determines which of a plurality of different possible authorization statuses is applicable for the received information segment for each of the respective authorization signals related to the different service providers; selects one of the determined statuses in accordance with a predetermined priority; selects from a plurality of different possible authorization status messages the message applicable to the status determined in accordance with said priority; and provides the selected message for display.

Abstract: A field-reprogammable storage control device has a microcontroller, a write-protected memory which contains a boot code for the storage control device, a rewriteable memory for application code executable by the microcontroller, and a jump function located in both the write-protected memory and the rewriteable memory for movement between the write-protected memory and the rewriteable memory for recover after a processing interruption. The storage control device remains operational using the write-protected memory and the boot code while receiving a new application code from a remote site.

Abstract: A software management system of an intelligent power conditioner with backup system option employing trend analysis for early prediction of AC power line failure. An AC line power conditioner utilizing a microprocessor based control system for providing suitable alarms when an operating input AC line is defective or the trend of measured deficiencies predicts line power failure and for initiating an inverter control signal when an inverter module is attached as an option. The software controlled system analyzes the input and output voltages, provides analysis of input voltage surges and sags, measures transient amplitude and transient pulse width, counts glitches and dropouts, measures frequency, and identifies each defect and computes associated trends, stores all accumulated data in a Log Buffer for digital printout, and then provides appropriate alarms to a user.

Abstract: A system for verifying the accuracy of stored data in a computer system where read and write requests can pass earlier-issued read and write requests. The system monitors read and write requests for a variety of data storage locations. When the system detects the first request to write data to a particular location it creates a data structure to represent that location and stores the data. For later write requests to the same location, the system modifies the data structure to store the new data being written, maintaining storage for only the data which can possibly be returned accurately for a read request. The system also monitors responses to read and write requests. For data returned in response to satisfaction of a read request, the system uses the data structure to determine if the returned data is accurate (i.e., if it is among the stored data). If the system determines that the returned data is inaccurate, it issues an error.

Abstract: A control system for preventing the occurrence of unsafe operating conditions on an appliance load comprises first and second switch elements coupled to said appliance load; first controller means coupled to said first switch element for detecting a first predetermined fault condition and producing a first fault detection signal in response to said detection of said predetermined fault condition, said first fault detection signal deactivating said first switch element and de-energizing said load; and second controller means coupled to said second switch element for detecting a second predetermined fault condition and producing a second fault detection signal in response to said detection of said predetermined fault condition, said second fault detection signal deactivating said second switch element and de-energizing said load.

Abstract: Disclosed is a system for communication among a device, a first processor, and a second processor. One of a first data path and second data path is configured. The first data path comprises a bus, such as a local PCI bus, a first remote bridge, and a first local bridge. The bridges may be comprised of PCI to PCI bridges. After configuring the first data path, the device communicates to the first processor by communicating data through the bus to the first remote bridge. The first remote bridge transmits the data to the first local bridge and the first local bridge transmits the data to the first processor. The second data path comprises the bus, a second remote bridge, and a second local bridge. After configuring the second data path, the device communicates to the second processor by communicating data through the bus to the second remote bridge. The second remote bridge transmits the data to the second local bridge and the second local bridge transmits the data to the second processor.

Abstract: A device for setting initializing data for every destination in an electronic device has a microcomputer for controlling the electronic device and an external memory connected to the microcomputer.

Abstract: A computer system having a processor is provided with a memory controller serially coupled to a serial-access programmable ROM (PROM) through the serial PROM interface of the controller. The random-access memory controller randomly accesses the BIOS code in the serial PROM during power-up of the computer system in response to read requests from the CPU. If the memory controller cannot immediately process the read requests from the CPU, the controller creates wait states for the CPU. The auto-configuring memory controller sequentially accesses the entire BIOS code in the serial PROM during power-up and prior to the running of the CPU, and copies it to a portion of base memory eliminating random accesses to the PROM.

Abstract: The object of the present invention is to balance power saving and useability in a computer system. According to a first aspect of the present invention, when predetermined activities of a device in a computer system, each of which occurs within a predetermined period t.sub.1 after the previous predetermined activity, succeed for a predetermined period t.sub.2 or longer, a substantial frequency of a central processing unit is raised. According to a second aspect of the present invention, a substantial frequency of the CPU is raised after a disk drive has been accessed, and if a predetermined activity performed by a device other than the disk drive occurs within a predetermined period t.sub.4 following the raise of the frequency, the substantial frequency of the CPU is lowered when a predetermined period t.sub.3, following the predetermined activity, has passed.

Abstract: A video controller for automatically varying a memory clock frequency according to the number of commands of controlling a memory includes: a video memory for storing image data to be transmitted to a monitor, a bus interface for receiving commands transmitted from a central processing unit (CPU) through a host bus, a controller for generating an address, data and a control signal for controlling reading from and writing into the video memory according to the commands received from the bus interface, a frequency setter for variably setting a memory clock frequency for accessing a video memory according to an occupancy rate of video access cycles with respect to total bus cycles, and a frequency generator for generating a memory clock according to the memory clock frequency set by the frequency setter.

Abstract: A method is provided for selecting a bootstrap processor from among the processors of a multiprocessor system. Each processor has an identity code and each processor that is eligible to serve as the bootstrap processor sends an election message to processors having lower valued identity codes. If no processor having a lower valued identity code responds to the election message, the processor that originated the election message designates itself as the bootstrap processor and sends a message to all processors indicating itself as the bootstrap processor.

Abstract: A communication terminal stores an assigned telephone number and a number unique to the terminal. When on-line registration is to be conducted with respect to a server, a registration screen is automatically created. On the registration screen, predetermined information is already described as entry matters required for registration by using the above described numbers. By inputting a password to this screen, the user can complete on-line registration simply. When the server provides service, the server requests the user to input the user name and the password. As for the communication terminal, the server has beforehand the telephone number, information unique to the terminal, and the like in the database. In response to a communication request from the communication terminal, the server conducts authentication by using the telephone number as the user name and the terminal number as the password.

Abstract: The present invention comprises a host bus clocked in a host clock domain, a secondary bus for receiving a reset command clocked in a secondary bus clock domain and a controller for dynamically delaying transactions on the host bus until the secondary bus is out of reset.

Abstract: When installing an operating system into a system-resident volume, the operating system boot path information and identifier are written into a backup memory and the system-resident volume. When booting of an operating system is instructed in the case in which the operating system has been installed on the system-resident volume of another computer, if a referencing means judges that the operating system boot path information and identifier have not been stored in the backup memory, a booting means causes the contents of the backup memory to coincide with the boot path information and the identifier that are stored in the system-resident volume, and then boots the operating system.

Abstract: A computer network includes a plurality of clients coupled to a server. The server includes data storage that stores network administration software and a shared client operating system. In response to detection of a new client attached to the computer network that has not previously been attached, the network administration software boots the shared client operating system on the new client. In one embodiment, the network administration software boots the shared client operating system on the new client in response to obtaining user logon information, where the user logon information is the only user input required for the network administration software to boot the shared client operating system on the new client.

Abstract: An information flow control means for location between a first and second computer network where the first network has a higher security classification than the second network. The information flow control means comprises an information switch having an information input, a first output connected to the first network, a second output connected to the second network, a controller having at least two states, a first state controlling the information switch to connect the input to the first output and a second state controlling the information switch to connect the input to the second output, and an information diode having an input for receiving information from the second network and an output for transferring information received from the second network to the first network through a connection from the information diode output to the first network and which prevents information flowing from the output to the input.

Abstract: A method and a system for estimating an assembling-related fraction defective coefficient of an article in the stage preceding to manufacturing, e.g. at a stage of design. Assembling operation, properties/conditions of parts to be assembled and conditions of an assembling shop having significant influence to the likelihood of occurrence of failure in assembling work are inputted as data. Estimated value of assembling-related fraction defective is arithmetically determined with high accuracy by executing an assembling-related fraction defective value estimating program on the basis of the data as inputted.

Abstract: A method and system for allocating programming objects of a control program configured to control a distributed control system having a plurality of distributed control modules. A graph model of the distributed control system is constructed which represents all the possible allocations of the control program's virtual programming objects to the processing resources associated with the system's control modules. A maximum matching algorithm is applied to the graph model to determine an optimum allocation, which, for instance, may be the allocation that provides the maximum benefit. The system and method also provide for intervention by the user to refine or "tune" the allocation process.

Abstract: A method and system for tracking and identifying food products as they are being processed is disclosed, wherein no tags or encodings are attached to the food products, and wherein there is no extraneous manipulation of the food products. The tracking system of the present invention utilizes sensor input from substantially any sensor capable of detecting a food product in some manner. That is, the tracking system uses binary detect/no detect inputs for determining whether a food product can be identified at each sensor along a predetermined path. Thus, given that a food product has been identified at a particular sensor, the tracking system generates an hypothesis indicative of when the food product is expected to be at the next sensor along the predetermined path. Accordingly, if the next sensor detects a food product within an allotted window, then the food product detected is assumed to be the one to which the hypothesis applies.