Abstract: A system and method for automatically tuning a PID controller resident within a PID control loop. The PID control loop includes a PID controller and a process. The process supplies a process variable which is compared to the loop input. The result of the comparison is supplied to the PID controller, and the PID controller drives the process. A relay is applied to the loop input. The relay compares a set point value to the process variable. If the set point value is greater than the process variable, the relay drives the loop input with a first amplitude value. If the set point value is less than the process variable, the relay drives the loop input with a second amplitude value. In response to the set point relay, the process variable develops a sustained oscillation. The period and amplitude of the sustained oscillation are measured. A new set of PID controller parameters are calculated from the period and amplitude of sustained oscillation.

Abstract: A computer having multi booting function with more than two boot-ROMs is disclosed. The boot-ROMs comprise a flash RAM, and have the same address space in the computer system. Preferably, the first boot-ROM is provided with a general boot program, and the second boot-ROM with detailed diagnostic program. Alternatively, the first boot-ROM is provided with a conventional boot program, and the second boot-ROM with reprogrammed or updated boot programs. Provided is a select signal generator for producing select signals which designate one of said boot-ROMs and a boot-ROM select circuit for producing control signals that selectively activate one boot-ROM in response to the memory control signals fed from the CPU and one of said select signals. The select signal generator includes a first and second reset switches for producing a first and second chip select signals, each designating the first and second boot-ROMs.

Abstract: A method for testing an IDE controller with random constraints, the method comprising: providing an IDE controller model having a primary and a secondary channel and a host interface; transmitting data patterns to a primary and a secondary device model; receiving the data patterns from the primary and secondary device models; arbitrating the transfer of the data patterns to and from the primary and secondary device models; and determining whether the data patterns returned from the primary and secondary device models match expected values.

Abstract: A hardware-based system for configuring a CPU and chip set logic of a computer system to allow data transfers on both the rising and falling edges of a bus clock signal. The CPU and chip set logic each include bus communication circuitry for transferring data, a storage unit, and a configuration circuit. The contents of the storage unit determine whether the respective bus communication circuitry transfers data on only one or on both clock edges. Initially, the bus communication circuits transfer data on only one clock edge. The configuration circuits of the CPU and chip set logic are connected by a single signal line and participate in a serial exchange of signals over the single signal line. The configuration circuits modify the contents of the respective storage units dependent upon an outcome of the serial exchange of signals. The configuration circuit of the CPU initiates the exchange of signals, transmitting a query signal.

Abstract: A tractable architecture level coverage measure uses information about the coverage measures obtained by the data path blocks, control logic blocks and cache to obtain an overall measure of coverage. This technique is applicable to a variety of different designs using different fabrication processes. Moreover, it allows the use of extended length test vectors, for example, such as those using commercial software applications. Since the coverage measure does not rely on the traditional stuck at model, it is applicable to extended length test vectors that may be used with high performance systems.

Abstract: A method for authenticating digital storage devices, including compact discs, CD-Roms, DVDs and floppy discs, is provided. A predetermined "fingerprint" code is embedded in one or more of the parity bytes which are always appended to the end of data frames for the purpose of detecting and correcting errors in the data frames as they are read from the digital storage devices by playback devices, such as CD players, computers, and DVD players. The "fingerprint" code is embedded during the mastering process of the originally-produced, authentic storage device by a "fingerprint" encoder implemented by either hardware or software. The "fingerprint" is not transferred to target storage devices when the original storage device is copied because standard duplicating equipment do not have the "fingerprint" encoder which will be used by mastering equipment.

Abstract: The invention relates to a process for synchronizing a computer system with regard to a date which changes over time. The computer system comprises one or more modules (1, 2, 3, 4), each module (1, 2) comprising several processors (10, 11, 12, 13, 20, 21, 22, 23) regulated by a clock specific to a module (1, 2). Each processor (10, 11, 12, 13, 20, 21, 22, 23) comprises a private register TBR (16, 17, 18, 19, 26, 27, 28, 29) adapted to contain a value corresponding to said date and to undergo an incrementation by the clock specific to the module (1, 2) comprising this processor (10, 11, 12, 13, 20, 21, 22, 23).

Abstract: A TAP linking module (21, 51) permits plural TAPs (TAPs 1-4) to be controlled and accessed from a test bus (13) via a single TAP interface (20).

Abstract: A clock signal generator within an electronic device locally generates a reference clock signal having a reference frequency from a base clock signal having a base frequency. The base clock signal is from a base signal source that is external to the electronic device, and the base frequency of the base clock signal may vary depending on the base signal source. The present invention includes a plurality of frequency dividers which are coupled to the base signal source. Each of the frequency dividers outputs a divided clock signal having a respective frequency that is the base frequency divided by a respective factor. A multiplexer accepts the value of the base frequency of the base clock signal as stored within a storage device that is external to the electronic device. The multiplexer then selects as the reference clock signal a divided clock signal having a respective frequency that is closest to the reference frequency depending on the value of the base frequency.

Abstract: A configuration apparatus for network devices. A plurality of LEDS on the front panel of a network device has a primary mode, displaying device and port status. These LEDS are grouped in a matrix, consisting of pairs of LEDS arranged in a plurality of parallel columns. Textual information may be provided adjacent each of the pairs, to describe an associated secondary mode, for configuration of the features and operational states of the device. When a configuration switch and mode control circuitry are enabled, drivers for the LEDS are disconnected from the ports. A configuration cycle is initiated, during which at least some of the LEDS provide visual cues to the user for carrying out the configuration operations. Sequential and unison blinking of the LEDS, as a group, individually, and in pairs, confirms reconfiguration opportunity, selection, and execution, for each secondary function.

Abstract: A signal processor sends clock and data signals from a microcomputer via two lines to two ICs of the same configuration. The ICs each have a built-in circuit for discriminating between the clock and data signals. This avoids the necessity of fabricating two kinds of ICs of different addresses, and hence obviates the need for forming extra masks in their manufacturing process, cutting their production costs.

Abstract: A system for booting a multi-processor computer. If a normal boot attempt fails, different processors are selected, one-at-a-time, for performing the boot routine. During the boot routing, all other processors are held inactive. After boot, processors are tested for health. Non-healthy processors are held inactive, and healthy processors are activated as usual.

Abstract: The invention concerns data transfer carried out by a communication network. It concerns in particular a method for safe data transfer by a communication network, between a first entity consisting of a chip card and a second entity, which consists in the preliminary production of an electronic signature for proving the initialisation of the transfer, this signature being stored in at least a memory zone of the chip card, then, when the data transfer is completed, in erasing this signature. The invention is applicable to electronic purses.

Abstract: A microprocessor 10 has an internal program memory 23 and direct memory access (DMA) circuitry 100. Microprocessor 10 also has provisions for connecting to an external source of data via an external bus 73. Configuration circuitry 74 or 81 provides configuration parameters to DMA 100 when a reset signal 76 is deasserted. DMA 100 boot loads microprocessor 10 by transferring a block of data which contains an initial program from an external source to internal program memory after reset signal 76 is deasserted. At the completion of the boot load, microprocessor begins execution of the initial program.

Abstract: A method of booting a portable computing device or a personal digital assistant (PDA) is described. In one embodiment, the PDA comprises a boot ROM, a RAM, and a connector for connecting to an external floppy disk drive (FDD). Operating system software and application software for the PDA is stored on a disk in FDD. To boot the PDA, the PDA is connected to the external FDD, then powered up. The PDA is hardwired to begin executing code from the boot ROM, which contains a program to transfer code from the FDD to the RAM, then jump to an entry point in the newly loaded code in the RAM. The PDA is then disconnected from the FDD. To configure the PDA with different operating system and/or different application software, the FDD is loaded with a disk storing this different software and the boot process is repeated. Thus, the PDA can be configured to support any number of different operating systems and any number of different applications despite having a limited capacity of RAM.

Abstract: A method of transferring firmware to a non-volatile memory of a programmable controller system comprises the steps of establishing a remote network connection and transferring the firmware to the non-volatile memory of the programmable controller system by way of the remote network connection. The remote network connection is established between a first computer system utilized by a firmware provider and the programmable controller system. The first computer system is located remotely from the programmable controller system. Alternatively, the remote network connection may also be established between the first computer system and a second computer system utilized by a user of the programmable controller system and located locally with the programmable controller system. Advantageously, using a network link, firmware upgrade can be downloaded into a processor module of a programmable controller system from a firmware provider, without any transportation delays and without any significant hardware intervention.

Abstract: A device driver initiates a DMA transfer and repeatedly reads a semaphore from a specified location in system memory. Upon completion of a DMA transfer, a DMA controller writes a semaphore containing status information to the specified location in system memory, informing the device driver that the DMA transfer is completed. A cache memory for the specified location in system memory is provided to further reduce the latency between DMA transfers.

Abstract: In an SMP computer system where data is partitioned across one or more chips a circuit and method permits detecting errors across chip boundaries due to a control error even though the ECC is not bad. A Multiple-input Shift-Register (MISR) on each bus is used to collect a dynamic signature representing all the critical buses on each chip that need to be compared. The MISR state combines present and previous states of these buses, so the MISR will be different if one or more bus controls break. Since an N-bit MISR shifts, comparing a single bit of the MISR each cycle guarantees detection within N cycles of a problem. The method of identifying errors includes accumulating bus signature information which is a function of current and previous values of an input bus and then comparing portions of the signatures of two or more input bus structures to determine sync of buses. Part of the signature is wrapped around into the signature to cause past information to be maintained indefinitely.

Abstract: A multimedia system including a PCI bus master controller for transferring concurrent and independent video and audio data streams to video and audio devices. The controller includes a video request and DMA channel, a video sub-picture request and DMA channel, an audio request and DMA channel, and a decompressed video DMA and posted request channel for independently and concurrently transferring the data streams from host memory to the devices. The host processor builds lists of request packets in system memory and asynchronously submits the request packets to the controller. The request packets include commands which the request channels execute. The commands may include spinning on status conditions in registers of the multimedia devices, writing to registers of the devices, or performing bus master transfers of multimedia data streams from system memory to the devices. The device register accesses are performed by the controller on local buses thereby reducing PCI bus traffic.

Abstract: A system for monitoring a computer system with an external status monitor during the power-on self test (POST) of the computer system. The computer system has tasks to be performed during the POST process. Each task has a token corresponding to an original message or a subsequently added message. Each subsequently added message is stored in the computer system, and each original message is stored in the external status monitor. Under the control of the computer system, the system identifies a task for the computer system to perform. The system then retrieves the token for the identified task and determines whether the retrieved token corresponds to an original message or a subsequently added message. If the retrieved token corresponds to an original message, the system sends only the retrieved token to the external status monitor.