Abstract: Organic electroluminescent devices and components containing the organic electroluminescent devices are provided herein. The organic electroluminescent devices include a substrate, a first light emitting unit, a second light emitting unit, a first electrode, and a second electrode. The light emitting units are positioned between the first and second electrode. The light emitting units have light emitting regions containing various emitter materials.

Abstract: In aspects of the assembly jig and method of the invention, when a packaging substrate is curved concaving upward at temperatures of melting solder, the gap between the assembly jig and the packaging substrate can be made smaller than the dimension of the sum of the thickness of the semiconductor chip and the thickness of the melted solder by allowing a part of the bottom surface of the chip positioning piece to become always, or substantially always, in contact with the upper surface of the packaging substrate owing to the weight of the chip positioning jig itself. As a consequence, the semiconductor chip does not slip aside out of the opening of the chip positioning piece. Therefore, the semiconductor chip can be positioned accurately on the packaging substrate.

Abstract: A display device includes an array substrate, a driving film and an adhesive member. The array substrate includes a first base substrate, a plurality of first signal pads formed on the first base substrate and a first dummy pad formed adjacent to the first signal pads. The driving film includes a base film, a plurality of output terminals formed on the base film and a first alignment mark formed adjacent to the output terminals. The adhesive member adheres the first signal pads to the output terminals, and adheres the first dummy pad to the first alignment mark.

Abstract: A system-on-chip device comprises a first capacitor in a first region, a second capacitor in a second region, and may further comprise a third capacitor in a third region, and any additional number of capacitors in additional regions. The capacitors may be of different shapes and sizes. A region may comprise more than one capacitor. Each capacitor in a region has a top electrode, a bottom electrode, and a capacitor insulator. The top electrodes of all the capacitors are formed in a common process, while the bottom electrodes of all the capacitors are formed in a common process. The capacitor insulator may have different number of sub-layers, formed with different materials or thickness. The capacitors may be formed in an inter-layer dielectric layer or in an inter-metal dielectric layer. The regions may be a mixed signal region, an analog region, and so forth.

Abstract: When forming sophisticated high-k metal gate electrode structures in an early manufacturing stage, superior process robustness, reduced yield loss and an enhanced degree of flexibility in designing the overall process flow may be accomplished by forming and patterning the sensitive gate materials prior to forming isolation regions.

Abstract: Structures and methods of forming crack stop trenches are disclosed. The method includes forming active regions disposed in cell regions of a substrate, the cell regions separated by dicing channels, and forming back end of line (BEOL) layers over the substrate, the BEOL layers being formed over the cell regions and the dicing channels. Crack stop trenches are then formed encircling the cell regions by etching a portion of the BEOL layers surrounding the cell regions. The wafer is diced along the dicing channels.

Abstract: A vertical interconnect architecture for a three-dimensional (3D) memory device suitable for low cost, high yield manufacturing is described. Conductive lines (e.g. word lines) for the 3D memory array, and contact pads for vertical connectors used for couple the array to decoding circuitry and the like, are formed as parts of the same patterned level of material. The same material layer can be used to form the contact pads and the conductive access lines by an etch process using a single mask. By forming the contact pads concurrently with the conductive lines, the patterned material of the contact pads can protect underlying circuit elements which could otherwise be damaged during patterning of the conductive lines.

Abstract: A method for forming a non-volatile memory device includes disposing a junction layer comprising a doped silicon-bearing material in electrical contact with a first conductive material, forming a switching layer comprising an undoped amorphous silicon-bearing material upon at least a portion of the junction layer, disposing a layer comprising a non-noble metal material upon at least a portion of the switching layer, disposing an active metal layer comprising a noble metal material upon at least a portion of the layer, and forming a second conductive material in electrical contact with the active metal layer.

Abstract: A method for forming a triple gate of a semiconductor device is provided. The method includes: forming a buffer layer and a hard mask over a substrate; etching the hard mask and the buffer layer to form a hard mask pattern and a buffer pattern; forming first and second trenches spaced apart within the substrate by partially etching the substrate by a vapor etching process using the hard mask pattern as an etching barrier layer; forming a buried insulation layer to fill the first and second trenches; removing the hard mask pattern and the buffer pattern; forming a gate insulation layer over the substrate between the first trench and the second trench; forming a conductive layer to cover the gate insulation layer; and etching the conductive layer to form a gate electrode.

Abstract: Methods are provided for forming a capacitor. In one embodiment, a method comprises providing an insulator material layer over a substrate, etching at least one via in the insulator material layer and depositing a contact material fill in the at least one via to form a first set of contacts. The method further comprises etching the insulator material layer adjacent at least one contact of the first set of contacts to form at least one void, depositing a dielectric material layer over the at least one void and over the first set of contacts and depositing a contact material fill in the at least void to form a second set of contacts.

Abstract: A method for manufacturing a silicon-based thin film solar cell including a crystalline silicon photoelectric conversion unit which contains a p-type layer (4p), a crystalline i-type silicon photoelectric conversion layer (4ic), and an n-type layer (4nc) stacked in this order from a transparent substrate side is provided. In one example, an n-type silicon-based thin film layer (4na) is formed on the crystalline i-type silicon photoelectric conversion layer (4ic), the n-type silicon-based thin film layer (4na) having an n-type silicon alloy layer having a film thickness of 1-12 nm and being in contact with the crystalline i-type silicon photoelectric conversion layer.

Abstract: Disclosed is a non-volatile, ferroelectric random access memory (F-RAM) device and a method for fabricating a damascene self-aligned F-RAM that allows for the formation of a ferroelectric capacitor with separated PZT layers aligned with a preexisting, three dimensional (3-D) transistor structure.

Abstract: Disclosed is a non-volatile, ferroelectric random access memory (F-RAM) device and a method for fabricating the same in the form of a damascene self-aligned F-RAM device comprising a PZT capacitor built on the sidewalls of an oxide trench, while allowing for the simultaneous formation of two ferroelectric sidewall capacitors.

Abstract: A wafer containing a plurality of electro-optical devices, each device being enclosed in chamber that has a translucent cover. An X-Y matrix of pairs of interconnections on the wafer are connected to the circuitry of the electro-optical devices for addressing the electro-optical devices. The pairs of interconnections extend outside of the chambers enclosing the devices to testing areas on the periphery of the wafer. Testing is done by signals applied through the interconnections while simultaneously exposing the devices to light through the translucent covers.

Abstract: Methods for making growth templates for the epitaxial growth of compound semiconductors and other materials are provided. The growth templates are thin layers of single-crystalline materials that are themselves grown epitaxially on a substrate that includes a thin layer of sacrificial material. The thin layer of sacrificial material, which creates a coherent strain in the single-crystalline material as it is grown thereon, includes one or more suspended sections and one or more supported sections.

Abstract: A replaceable chamber element for use in a plasma processing system, such as a plasma etching system, is described. The replaceable chamber element includes a chamber component configured to be exposed to plasma in a plasma processing system, wherein the chamber component is fabricated to include a semiconductor junction, and wherein a capacitance of the chamber component is varied when a voltage is applied across the semiconductor junction.