Abstract: An LED module is disclosed containing an integrated driver transistor (e.g, a MOSFET) in series with an LED. In one embodiment, LED layers are grown over a substrate. The transistor regions are formed over the same substrate. After the LED layers, such as GaN layers, are grown to form the LED portion, a central area of the LED is etched away to expose a semiconductor surface in which the transistor regions are formed. A conductor connects the transistor in series with the LED. Another node of the transistor is electrically coupled to an electrode on the bottom surface of the substrate. In one embodiment, an anode of the LED is connected to one terminal of the module, one current carrying node of the transistor is connected to a second terminal of the module, and the control terminal of the transistor is connected to a third terminal of the module.

Abstract: To provide a highly reliable semiconductor device by giving stable electrical characteristics to a transistor including an oxide semiconductor film. A gate electrode layer is formed over a substrate, a gate insulating film is formed over the gate electrode layer, an oxide semiconductor film is formed over the gate insulating film, a conductive film is formed over the oxide semiconductor film, so that a region in vicinity of an interface with the oxide semiconductor film in contact with the conductive film is made amorphous, heat treatment is performed, the conductive film is then processed to form a source electrode layer and a drain electrode layer, and a part of the amorphous region in the oxide semiconductor film which is exposed by formation of the source electrode layer and the drain electrode layer is removed.

Abstract: Two series-connected metal-insulator-metal (MIM) capacitors are disclosed that are suitable for fabrication in the back-end structure of an integrated circuit. The MIM capacitors have first and second electrically conducting plates on a first insulating layer, third and fourth electrically conducting plates overlapping the first and second conducting plates, a second insulating layer between the first and third conducting plates and between the second and fourth conducting plates, a blind via coupling the first and fourth conducting plates, and connections to the second and third conducting plates. Methods of fabricating such series-connected MIM capacitors are also disclosed.

Abstract: A display device includes a first substrate and a second substrate facing each other, a thin film transistor on the first substrate, a color filter and a black matrix on the first substrate, a column spacer on the first substrate and electrically connected to the thin film transistor, a pixel electrode on one surface of the second substrate, a common electrode on the pixel electrode on the one surface of the second substrate, and a transparent electrode on the other surface of the second substrate. The column spacer is electrically connected to the pixel electrode.

Abstract: An integrated circuit includes four electronic components, a buried UTBOX layer under and plumb with the electronic components, and two pairs of oppositely doped ground planes plumb with corresponding components under the layer. A first isolation trench mutually isolates the ground planes from corresponding wells made plumb and in contact with the ground planes and exhibiting the first doping type. Bias electrodes contact respective wells and ground planes. One pair of electrodes is for connecting to a first bias voltage and the other pair is for connecting to a second bias voltage. Also included are a semiconductor substrate exhibiting the first type of doping and a deeply buried well exhibiting the second type of doping. The deeply buried well contacts the other wells and separates them from the substrate. Finally, a control electrode couples to the deeply buried well.

Abstract: In a light emitting module 40, a light wavelength conversation ceramic 52 converts the wavelength of the light emitted by a semiconductor light emitting element 48 then emits the light. An optical filter 50 transmits the blue light Lb mainly emitted by the semiconductor light emitting element 48 and reflects the yellow light Ly whose wavelength has been mainly converted by the light wavelength conversion ceramic 52. The optical filter 50 is provided on the surface of the light wavelength conversion ceramic 52. The light emitting module 40 is manufactured by: the process where the optical filter 50 is provided on at least one surface of the light wavelength conversion ceramic 52; and the process where the semiconductor light emitting element 48 and the light wavelength conversion ceramic 52 are arranged such that the light emitted by the semiconductor light emitting element 48 is incident into the light wavelength conversion ceramic 52.

Abstract: LED modules are disclosed having a control MOSFET, or other transistor, in series with an LED. In one embodiment, a MOSFET wafer is bonded to an LED wafer and singulated to form thousands of active 3-terminal LED modules with the same footprint as a single LED. Despite the different forward voltages of red, green, and blue LEDs, RGB modules may be connected in parallel and their control voltages staggered at 60 Hz or greater to generate a single perceived color, such as white. The RGB modules may be connected in a panel for general illumination or for a color display. A single dielectric layer in a panel may encapsulate all the RGB modules to form a compact and inexpensive panel. Various addressing techniques are described for both a color display and a lighting panel. Various circuits are described for reducing the sensitivity of the LED to variations in input voltage.

Abstract: An image pickup apparatus includes a pixel portion in which pixels are arranged, the pixels each including a first semiconductor region of first conductivity type having signal charges as majority carriers and a second semiconductor region of second conductivity type having signal charges as minority carriers, the second semiconductor region being contiguous to the first semiconductor region, the first semiconductor region being disposed between a surface of a semiconductor substrate. The pixel portion includes a class I pixel and a class II pixel located near a reference contact. A distance between the surface of the semiconductor substrate and the second semiconductor region of the class I pixel is smaller than a distance between the surface of the semiconductor substrate and the second semiconductor region of the class II pixel.

Abstract: A method of forming an integrated circuit structure includes providing a gate stack and a gate spacer on a sidewall of the gate stack. A contact etch stop layer (CESL) is formed overlying the gate spacer and the gate stack. The CESL includes a top portion over the gate stack, a bottom portion lower than the top portion, and a sidewall portion over a sidewall of the gate spacer. The top and bottom portions are spaced apart from each other by the sidewall portion. The sidewall portion has a thickness less than a thickness of the top portion or a thickness of the bottom portion.

Abstract: A method of making a gate structure includes forming a trench in a dielectric layer. The method further includes forming a gate dielectric layer in the trench. The gate dielectric layer defines an opening in the dielectric layer. The method includes forming a gate electrode in the opening. Forming the gate electrode includes filling a width of a bottom portion of the opening with a first metal material. The first metal material has a recess. Forming the gate electrode includes filling an entire width of a top portion of the opening with a homogeneous second metal material. The homogeneous second metal material has a protrusion extending into the recess, and a maximum width of the homogeneous second metal material is equal to a maximum width of the first metal material. A top surface of the gate dielectric layer is co-planar with a top surface of the homogeneous second metal material.

Abstract: A method of forming an interconnect structure of an integrated circuit including providing a first dielectric layer disposed on a semiconductor substrate. A via (or via hole) is etched in the first dielectric layer. A conductive layer including copper is formed that fills the via hole and has a first portion that is disposed on a top surface of the first dielectric layer. A trench is formed in the first portion of the conductive layer to pattern a copper interconnect line disposed on the first dielectric layer. The trench is filled with a second dielectric material. In an embodiment, a barrier layer is self-formed during the removal of a masking element used in the etching of the trench.

Abstract: By reducing the contact resistance between an oxide semiconductor film and a metal film, a transistor that uses an oxide semiconductor film and has excellent on-state characteristics is provided. A semiconductor device includes a pair of electrodes over an insulating surface; an oxide semiconductor film in contact with the pair of electrodes; a gate insulating film over the oxide semiconductor film; and a gate electrode overlapping with the oxide semiconductor film with the gate insulating film interposed therebetween. In the semiconductor device, the pair of electrodes contains a halogen element in a region in contact with the oxide semiconductor film. Further, plasma treatment in an atmosphere containing fluorine can be performed so that the pair of electrodes contains the halogen element in a region in contact with the oxide semiconductor film.

Abstract: The present disclosure provides a method of fabricating a semiconductor device that includes forming a plurality of fins, the fins being isolated from each other by an isolation structure, forming a gate structure over a portion of each fin; forming spacers on sidewalls of the gate structure, respectively, etching a remaining portion of each fin thereby forming a recess, epitaxially growing silicon to fill the recess including incorporating an impurity element selected from the group consisting of germanium (Ge), indium (In), and carbon (C), and doping the silicon epi with an n-type dopant.

Abstract: An organic light emitting diode display device includes: a reflective electrode and an auxiliary electrode; a bank layer on the reflective electrode and the auxiliary electrode, the bank layer including a first open portion and a second open portion exposing a portion of the reflective electrode and a portion of the auxiliary electrode, respectively; a separator on the auxiliary electrode, the separator disposed within the second open portion; a pixel electrode in contact with the portion of the reflective electrode exposed by the first open portion of the bank layer, the pixel electrode being disposed separated from the separator; an organic emission layer on the pixel electrode, the organic emission layer divided by the separator, the organic emission layer being disposed separated from the separator; and a common electrode on the organic emission layer, the common electrode connected to the auxiliary electrode.

Abstract: A phase change memory cell includes a first circuit and a second circuit. The first circuit comprises a first electrode, a carbon nanotube layer and a second electrode electrically connected in series. The first circuit is adapted to write data into the phase change memory cell or reset the phase change memory cell. The second circuit comprises a third electrode, a phase change layer and a fourth electrode electrically connected in series, at least part of the phase change layer is overlapped with the carbon nanotube layer. The second circuit is adapted to read data from the phase change memory cell or reset the phase change memory cell.

Abstract: A semiconductor device includes: a substrate comprised by gallium arsenide; an active layer provided on the substrate; a first nickel-plated layer provided on a lower face of the substrate facing the active layer; a copper-plated layer provided on a lower face of the first nickel-plated layer; and a second nickel-plated layer provided on a lower face of the copper-plated layer.

Abstract: A semiconductor package includes a semiconductor substrate, a contact pad overlying the semiconductor substrate, an interconnect layer overlying the contact pad, a passivation layer formed between the contact pad and the interconnect layer, a bump overlying the interconnect layer, and a protection layer overlying the interconnect layer and the passivation layer and covering a lower portion of the bump. The protection layer includes a curved surface region.

Abstract: A light-emitting element includes: a light-emitting structure; a plurality of first contact portions separately on the light-emitting structure; and a plurality of reflective portions disposed separately among the plurality of first contact portions.

Abstract: The semiconductor device package includes a conformal shield layer applied to the exterior surface of the encapsulant, and an internal fence or separation structure embedded in the encapsulant. The fence separates the package into various compartments, with each compartment containing at least one die. The fence thus suppresses EMI between adjacent packages. The package further includes a ground path connected to the internal fence and conformal shield.

Abstract: A pixel of an organic light emitting display device includes a transistor configured to output a first source voltage, an organic light emitting diode coupled to the transistor, and a wiring configured to be applied with a reference voltage to ground a leakage current of the transistor. The organic light emitting diode includes a first electrode configured to receive the first source voltage, a first common layer on the first electrode, an organic light emitting layer on the first common layer, and a second electrode on the organic light emitting layer and configured to be applied with a second source voltage different from the first source voltage. The first common layer is coupled to the wiring.