Abstract: Embodiments of the present disclosure provide a method, comprising providing a semiconductor substrate having (i) a first surface and (ii) a second surface that is disposed opposite to the first surface, forming one or more vias in the first surface of the semiconductor substrate, the one or more vias initially passing through only a portion of the semiconductor substrate without reaching the second surface, forming a dielectric film on the first surface of the semiconductor substrate, forming a redistribution layer on the dielectric film, the redistribution layer being electrically coupled to the one or more vias, coupling one or more dies to the redistribution layer, forming a molding compound to encapsulate at least a portion of the one or more dies, and recessing the second surface of the semiconductor substrate to expose the one or more vias. Other embodiments may be described and/or claimed.

Abstract: Embodiments of the present invention provide for the provisioning of efficient support to semiconductor-on-insulator (SOI) structures. Embodiments of the present invention may additionally provide for SOI structures with improved heat dissipation performance while preserving the beneficial electrical device characteristics that accompany SOI architectures. In one embodiment, an integrated circuit is disclosed. The integrated circuit comprises a silicon-on-insulator die from a silicon-on-insulator wafer. The silicon on insulator die comprises an active layer, an insulator layer, a substrate, and a strengthening layer. The substrate consists of an excavated substrate region, and a support region, the support region is in contact with the insulator layer. The support region and the strengthening layer are configured to act in combination to provide a majority of a required stabilizing force to the silicon-on-insulator die when it is singulated from the silicon-on-insulator wafer.

Abstract: Embodiments of the present invention provide for the dissipation of heat from semiconductor-on-insulator (SOI) structures. In one embodiment, a method for fabricating an integrated circuit is disclosed. In a first step, active circuitry is formed in an active layer of a SOI wafer. In a second step, substrate material is removed from a substrate layer disposed on a back side of the SOI wafer. In a third step, insulator material is removed from the back side of the SOI wafer to form an excavated insulator region. In a fourth step, a thermal dissipation layer is deposited on said excavated insulator region. The thermal dissipation layer is thermally conductive and electrically insulating.

Abstract: Apparatus, systems, and methods are described to assist in reducing dark current in an active pixel sensor. In various embodiments, a potential barrier arrangement is configured to block the flow of charge carriers generated outside a photosensitive region. In various embodiments, a potential well-potential barrier arrangement is formed to direct charge carriers away from the photosensitive region during an integration time.

Abstract: An SRAM array and method of making is disclosed. Each SRAM cell comprises two pull-up (PU), two pass-gate (PG), and two pull-down (PD) FinFETs. The PU transistors are adjacent to each other and include one active fin having a first fin width. Each PG transistor shares at least one active fin with a PD transistor. The at least one active fin shared by a PG and a PD transistor has a second fin width smaller than the first fin width. The method includes patterning a plurality of fins including active fins and dummy fins and patterning and removing at least a portion of the dummy fins. No dummy fin is disposed between PU FinFETs in a memory cell. One dummy fin is disposed between a PU FinFET and the at least one active fin shared by a PG and a PD transistor. At least one dummy fin is disposed between adjacent memory cells.

Abstract: A semiconductor structure includes a substrate, a dielectric layer and a fluoride metal layer. The dielectric layer is located on the substrate. The fluoride metal layer is located on the dielectric layer. Furthermore, the present invention also provides a semiconductor process to form said semiconductor structure.

Abstract: A semiconductor die has an insulating material disposed in a peripheral region around the die. A blind via is formed through the gap. A conductive material is deposited in the blind via to form a conductive via. A conductive layer is formed between the conductive via and contact pad on the semiconductor die. A protective layer is formed over the front side of the semiconductor die. A portion of the insulating material and conductive via is removed from a backside of the semiconductor die opposite the front side of the semiconductor die so that a thickness of the conductive via is less than a thickness of the semiconductor wafer. The insulating material and conductive via are tapered. The wafer is singulated through the gap to separate the semiconductor die. A plurality of semiconductor die can be stacked and electrically interconnected through the conductive vias.

Abstract: III-N transistors with recessed gates. An epitaxial stack includes a doped III-N source/drain layer and a III-N etch stop layer disposed between a the source/drain layer and a III-N channel layer. An etch process, e.g., utilizing photochemical oxidation, selectively etches the source/drain layer over the etch stop layer. A gate electrode is disposed over the etch stop layer to form a recessed-gate III-N HEMT. At least a portion of the etch stop layer may be oxidized with a gate electrode over the oxidized etch stop layer for a recessed gate III-N MOS-HEMT including a III-N oxide. A high-k dielectric may be formed over the oxidized etch stop layer with a gate electrode over the high-k dielectric to form a recessed gate III-N MOS-HEMT having a composite gate dielectric stack.

Abstract: Methods of forming a metal silicide region in an integrated circuit are provided herein. In some embodiments, a method of forming a metal silicide region in an integrated circuit includes forming a silicide-resistive region in a first region of a substrate, the substrate having the first region and a second region, wherein a mask layer is deposited atop the substrate and patterned to expose the first region; removing the mask layer after the silicide-resistive region is formed in the first region of the substrate; depositing a metal-containing layer on a first surface of the first region and a second surface of the second region; and annealing the deposited metal-containing layer to form a first metal silicide region in the second region.

Abstract: A semiconductor device includes an insulated-gate field-effect transistor which is disposed on a semiconductor substrate having an element formation plane in a (110) plane direction, and which has a channel length direction in a <?110 > direction, and a first element isolation insulation film which is buried in a trench in an element isolation region of the semiconductor substrate and has a positive expansion coefficient, the first element isolation insulation film applying a compressive stress by operation heat to the insulated-gate field-effect transistor in the channel length direction.

Abstract: A light-emitting diode (LED) according to an exemplary embodiment includes a light-emitting structure arranged on a first surface of a substrate, the light-emitting structure including a first conductivity-type semiconductor layer, a second conductivity-type semiconductor layer, and an active layer interposed between the first conductivity-type semiconductor layer and the second conductivity-type semiconductor layer. A first distributed Bragg reflector is arranged on a second surface of the substrate opposite to the first surface, the first distributed Bragg reflector to reflect light emitted from the light-emitting structure. The first distributed Bragg reflector has a reflectivity of at least 90% with respect to blue, green, and red light.

Abstract: An organic light emitting device includes a first electrode and a second electrode, an organic layer including a light emitting layer between the first electrode and the second electrode, and an insulating film covering a rim of the first electrode from a surface thereof to a side surface thereof, and having an internal wall surface being in contact with the organic layer, and one or more corner sections in the internal wall surface with a ridge line thereof in parallel with the surface of the first electrode.

Abstract: A ferroelectric capacitor formed above a semiconductor substrate includes a lower electrode, a dielectric film (ferroelectric film) having ferroelectric characteristics, and an upper electrode. The upper electrode includes a conductive oxide film made of a ferroelectric material to which conductivity is provided by adding a conductive material such as Ir, and the conductive oxide film is in contact with the dielectric film.

Abstract: A liquid crystal display device includes a gate line on a substrate including a display region and a non-display region; odd and even data lines crossing the gate line to define a pixel region in the display region; a thin film transistor connected to the gate line and one of the odd and even data lines; a pixel electrode in the pixel region and connected to the thin film transistor; first and second data link lines electrically connected to the odd and even data lines, respectively, and formed with a gate insulating layer therebetween; and first and second data pad electrodes at one ends of the first and second data link lines, respectively.

Abstract: Gray tone lithography is used to form curved silicon topographies for semiconductor based solid-state imaging devices. The imagers are curved to a specific curvature and shaped directly for the specific application; such as curved focal planes. The curvature of the backside is independent from the front surface, which allows thinning of the detector using standard semiconductor processing.

Abstract: A light emitting device includes: one or plural light emitting elements having plural electrodes; a chip-like insulator surrounding the one or plural light emitting elements from a side surface side of the one or plural light emitting elements; and plural terminal electrodes electrically connected one-to-one with the plural electrodes, and having protrusions each protruding from a peripheral edge of the chip-like insulator.

Abstract: The present invention relates to a plurality of light emitting diodes connected in series to elevate the working voltage and to enable the devices to be connected directly to the AC voltage sources. The LED device has five pluralities of series-connected diodes. Four pluralities of series-connected diodes are arranged to at as a rectifier bridge so the fifth plurality of diodes is always forward biased and energized. The light emitting diodes in the device are arranged to accommodate various AC line voltages, diode operating voltages, and diode reverse breakdown voltages. The plurality of diodes was manufactured by first etching epitaxial layer to the insulating substrate to isolate individual diodes, and then use metal lines to interconnect them according to the layout design. The number of die-attach and wire-bonding steps used in the subsequent chip array and lamp manufacturing process is therefore greatly reduced or eliminated.

Abstract: The micro-electromechanical device has a substrate. Integrated into the substrate is a micromechanical component that has a bending element which can be bent reversibly and which has a first end connected to the substrate and extends from the first end over a free space. The bending element has at least one web having two side edges, the course of which is defined by depressions introduced into the bending element and adjacent to the side edges. In order to form a homogenization region located within the web, in which mechanical stresses occurring during bending of the bending element are substantially equal, the mutual spacing of the side edges of the web decreases, as viewed from the first end of the bending element. The device further comprises at least one microelectronic component that is sensitive to mechanical stresses and embedded in the web in the homogenization region of the latter.

Abstract: A semiconductor device and a method for fabricating the semiconductor device are disclosed. A gate stack is formed over a substrate. A spacer is formed adjoining a sidewall of the gate stack. A recess is formed between the spacer and the substrate. Then, a strained feature is formed in the recess. The disclosed method provides an improved method by providing a space between the spacer and the substrate for forming the strained feature, therefor, to enhance carrier mobility and upgrade the device performance.

Abstract: A transistor device having a graphene base for the transport of electrons into a collector is provided. The transistor consists of a heterostructure comprising an electron emitter, an electron collector, and a graphene material base layer consisting of one or more sheets of graphene situated between the emitter and the collector. The transistor also can further include an emitter transition layer at the emitter interface with the base and/or a collector transition layer at the base interface with the collector. The electrons injected into the graphene material base layer can be “hot electrons” having an energy E substantially greater than EF, the Fermi energy in the graphene material base layer or can be “non-hot electrons” having an energy E approximately equal to than EF. The electrons can have the properties of ballistic transit through the base layer.