Abstract: A light-emitting element includes a light-emitting structure, a plurality of first contact portions disposed separately on the light-emitting structure, and a plurality of reflective portions disposed separately among the first contact portions.

Abstract: Embodiments of the present invention provide for the enhancement of transistors in a semiconductor structure using a strain layer. The structure comprises a patterned layer consisting of an excavated region and a pattern region, a strain layer located in the excavated region and on the pattern region, an active layer located above the strain layer, a field effect transistor formed in the active layer, and a handle layer located above the active layer. The field effect transistor comprises a source, a drain, and a channel. The channel lies completely within a lateral extent of the pattern region. The source and the drain each lie only partially within the lateral extent of the pattern region. The strain layer alters a carrier mobility of the channel. In some embodiments, the strain layer is introduced to the back side of a semiconductor-on-insulator structure.

Abstract: A method of making a gate structure includes forming a gate electrode in an opening defined by a gate dielectric layer having a top surface. Forming the gate electrode includes filling a width of a bottom portion of the opening with a first metal material having a first resistance. Forming the gate electrode further includes defining a recess in the first metal material. Forming the gate electrode further includes filling an entire width of a top portion of the opening and the recess with a homogeneous second metal material having a second resistance less than the first resistance, wherein a maximum width of the homogeneous second metal material is equal to a maximum width of the first metal material, and the top surface of the gate dielectric layer is co-planar with a top surface of the homogeneous second metal material.

Abstract: An SRAM array and method of making is disclosed. Each SRAM cell comprises two pull-up (PU), two pass-gate (PG), and two pull-down (PD) FinFETs. The PU transistors are adjacent to each other and include one active fin having a first fin width. Each PG transistor shares at least one active fin with a PD transistor. The active fin shared by a PG and a PD transistor has a second fin width smaller than the first fin width. The method includes patterning a plurality of fins including active fins and dummy fins and patterning and removing at least a portion of the dummy fins. No dummy fin is disposed between PU FinFETs in a memory cell. One dummy fin is disposed between a PU FinFET and the at least one active fin shared by a PG and a PD transistor. At least one dummy fin is disposed between adjacent memory cells.

Abstract: A phase change memory cell includes a carbon nanotube layer, a phase change layer, a first electrode, a second electrode, and a third electrode. At least part of the phase change layer is overlapped with the carbon nanotube layer. The first electrode and the second electrode are electrically connected with the carbon nanotube layer, wherein the first electrode and the second electrode are configured to apply a first voltage to the carbon nanotube layer. The third electrode is electrically connected with the phase change layer, wherein the third electrode and the first electrode are configured to apply a second voltage to the phase change layer.

Abstract: An image sensor device comprises an isolation well region within a substrate. A gate stack is over the isolation well region on the first surface of the substrate. The gate stack has an edge. A doped isolation feature is within the substrate between the isolation well region and the gate stack. The doped isolation feature surrounds an active area. The gate stack is over the active area. The doped isolation feature extends from the edge of the gate stack under the gate stack.

Abstract: A semiconductor device includes: a substrate comprised by gallium arsenide; an active layer provided on the substrate; a first nickel-plated layer provided on a lower face of the substrate facing the active layer; a copper-plated layer provided on a lower face of the first nickel-plated layer; and a second nickel-plated layer provided on a lower face of the copper-plated layer.

Abstract: The present invention provides a molded encapsulated multi-layered semiconductor device, comprising a first substrate, a second substrate and an anti-delamination structure (ADS). The ADS comprises a connecting part and extended structures, and is filled by an insulating material. The present invention is able to provide the molded semiconductor device with higher reliability and longer lifetime through reduction of shear stress generated from the coefficient of thermal expansion mismatch between a silicon die and the substrates by mechanically locking with the ADS.

Abstract: A polymerizable composition contains (A) a polymerization initiator that is an acetophenone-based compound or an acylphosphine oxide-based compound, (B) a polymerizable compound, (C) at least either a tungsten compound or a metal boride, and (D) an alkali-soluble binder.

Abstract: Embodiments of the present disclosure provide a method, comprising providing a semiconductor substrate having (i) a first surface and (ii) a second surface that is disposed opposite to the first surface, forming one or more vias in the first surface of the semiconductor substrate, the one or more vias initially passing through only a portion of the semiconductor substrate without reaching the second surface, forming a dielectric film on the first surface of the semiconductor substrate, forming a redistribution layer on the dielectric film, the redistribution layer being electrically coupled to the one or more vias, coupling one or more dies to the redistribution layer, forming a molding compound to encapsulate at least a portion of the one or more dies, and recessing the second surface of the semiconductor substrate to expose the one or more vias. Other embodiments may be described and/or claimed.

Abstract: A method performed using a resistive device, where the resistive device includes a substrate with an active region separated from a gate electrode by a dielectric and electrical contacts along a longest dimension of the gate electrode, the method comprising, performing one or more processes to form the resistive device, measuring a resistance between the electrical contacts, and correlating the measured resistance with a variation in one or more of the processes.

Abstract: In a light emitting panel, organic EL panels are laminated in a step-like shape in a front-back direction to form organic EL panel groups, and the organic EL panel groups are further laminated in a step-like shape in a left-right direction. Each of the organic EL panels comprises a power feed part at one side of the transparent support substrate in the left-right direction. The power feed part of each of the organic EL panels is aligned with other power feed parts in the front-back direction at one side of the left-right direction, and is disposed at a position that allows the power feed part to overlap with a laminate of an organic EL panel of an adjacent organic EL panel group.

Abstract: A system and method for fabricating a 3D image sensor structure is disclosed. The method comprises providing an image sensor with a backside illuminated photosensitive region on a substrate, applying a first dielectric layer to the first side of the substrate opposite the substrate side where image data is gathered, and applying a semiconductor layer that is optionally polysilicon, to the first dielectric layer. A least one control transistor may be created on the first dielectric layer, within the semiconductor layer and may optionally be a row select, reset or source follower transistor. An intermetal dielectric may be applied over the first dielectric layer; and may have at least one metal interconnect disposed therein. A second interlevel dielectric layer may be disposed on the control transistors. The dielectric layers and semiconductor layer may be applied by bonding a wafer to the substrate or via deposition.

Abstract: Disclosed are semiconductor packages and methods of forming the same. In the semiconductor packages and the methods, a package substrate includes a hole not overlapped with semiconductor chips. Thus, a molding layer may be formed without a void.

Abstract: The method includes forming an upper layer on a lower layer, forming a metal interconnection in the upper layer, forming a passivation layer exposing a center part of the metal interconnection on the upper layer, forming a buffer pattern exposing the center part of the metal interconnection, and selectively and asymmetrically covering a peripheral region of the metal interconnect and a part of the passivation layer, forming a wrapping pattern covering the buffer pattern and exposing the center part of the metal interconnection on the passivation layer, and forming a pad pattern on the center part of the metal interconnection.

Abstract: There is provided a polycrystalline aluminum nitride substrate that is effective in growing a GaN crystal. The polycrystalline aluminum nitride base material for use as a substrate material for grain growth of GAN-base semiconductors, contains 1 to 10% by weight of a sintering aid component and has a thermal conductivity of not less than 150 W/m·K, the substrate having a surface free from recesses having a maximum diameter of more than 200 ?m.

Abstract: An organic light emitting diode (OLED) display includes a substrate where a plurality of pixels are formed, a first pixel defining layer on the substrate, the first pixel defining layer dividing the plurality of pixels, a connection wire on the first pixel defining layer, the connection wire electrically connecting two adjacent pixels, and a second pixel defining layer on the first pixel defining layer, the second pixel defining layer covering the connection wire.

Abstract: A pixel array includes a plurality of first and second signal lines, a plurality of active devices, a plurality of pixel electrodes, a plurality of selection lines, and a plurality of protrusions. The second signal lines are electrically insulated to and intersected with the first signal lines. Each active device is electrically connected to one of the first signal lines and one of the second signal lines, respectively. The pixel electrodes are electrically connected to the active devices. The selection lines are electrically insulated to the second signal lines and intersected with the first signal lines so as to form a plurality of intersections including a plurality of first and second intersections. The selection lines are electrically connected to the first signal lines at the first intersections. The protrusions are disposed between the selection lines and the first signal lines, and located at the second intersections.

Abstract: The present disclosure provides a method of fabricating a semiconductor device that includes forming a plurality of fins, the fins being isolated from each other by an isolation structure, forming a gate structure over a portion of each fin; forming spacers on sidewalls of the gate structure, respectively, etching a remaining portion of each fin thereby forming a recess, epitaxially growing silicon to fill the recess including incorporating an impurity element selected from the group consisting of germanium (Ge), indium (In), and carbon (C), and doping the silicon epi with an n-type dopant.

Abstract: The invention relates to a substrate for producing a substrate-product substrate combination by aligning, bringing into contact, and bonding a contact side of the large-area substrate to a support surface of a carrier substrate, whereby the substrate has a diameter d1, which can be reduced during back-thinning.