Abstract: An analog-to-digital converter (ADC) configured to convert an analog signal to digital bits. The ADC includes a plurality of sub-ADCs that are cascaded in a pipeline. Each sub-ADC may be configured to sample an input signal that is fed to each sub-ADC and convert the sampled input signal to a pre-configured number of digital bits. Each sub-ADC except a last sub-ADC in the pipeline is configured to generate a residue signal and feed the residue signal as the input signal to a succeeding sub-ADC in the pipeline. At least one sub-ADC is configured to determine a most-significant bit (MSB) of the pre-configured number of digital bits while the input signal is sampled. The ADC may include a plurality of residue amplifiers for amplifying a residue signal. The sub-ADCs may be successive approximation register (SAR) ADCs or flash ADCs.

Abstract: A dipole antenna apparatus, and method of manufacture of such an apparatus, are provided. The antenna apparatus has a conductive plate extending in a first plane, and a pair of conductive elements arranged to form a dipole antenna, where the pair of conductive elements are located in a second plane parallel to the first plane. Each conductive element forms a conductive ring in the second plane that surrounds a non-conductive inner area. The first conductive element in the pair of conductive elements has a conductive bridge extending across the conductive ring to divide the non-conductive inner area into at least two portions. A conductive connection then extends from the conductive bridge to the conductive plate.

Abstract: Systems, apparatuses, and methods related to bit string compression are described. A method for bit string compression can include determining that a particular operation is to be performed using a bit string formatted according to a universal number format or a posit format to alter a bit width associated with the bit string from a first bit width to a second bit width and performing a compression operation on a bit string formatted according to a universal number format or a posit format to alter a bit width associated with the bit string from a first bit width to a second bit width. The method can further include writing the bit string having the second bit width to a first register, performing an arithmetic operation or a logical operation, or both using the bit string having the second bit string width, and monitoring a quantity of bits of a result of the operation.

Abstract: A data compressor includes a zero-value remover, a zero bit mask generator and a non-zero values packer. The zero-value remover receives 2N bit streams of values and outputs 2N non-zero-value bit streams having zero values removed from each respective bit stream based on a selected granularity of compression for values contained in the bit streams. The zero bit mask generator receives the 2N bit streams of values and generates a zero bit mask corresponding to the selected granularity of compression. Each zero bit mask indicates a location of a zero value based on the selected granularity of compression. The non-zero values packer receives the 2N non-zero-value bit streams and forms at least one first group of packed non-zero values.

Abstract: Examples of slot antennas are described herein. In an example, the slot antenna includes a substrate and an antenna element disposed on the substrate to transmit and receive signals. The substrate is porous.

Abstract: A wearable device comprises wireless communication means and a patch antenna that is coupled to said wireless communication means to receive and/or transmit electromagnetic radiation. Said patch antenna comprises a planar patch conductor and a planar ground conductor that are separated by a dielectric in between said patch conductor and said ground conductor while at least partially overlapping with one another. The device comprises a core inside a shell and comprises at least part of said communication means within said core. Said shell comprises a first shell part and a second shell part opposite said first shell part, wherein said first shell part and said second shell part are at least partially separated by said dielectric. Said first shell part comprises said patch conductor and said second shell part comprises said ground conductor. Said first shell part and said second shell part together form said patch antenna. The wearable device particularly is a piece of jewellery.

Abstract: An analog-to-digital converter (ADC) includes a comparator, a voltage reference circuit, a first capacitive digital-to-analog converter (CDAC), and a second CDAC. The first CDAC includes a plurality of capacitors. Each of the capacitors of the first CDAC includes a top plate coupled to a first input of the comparator, and a bottom plate switchably coupled to an output of the voltage reference circuit. The second CDAC includes a plurality of capacitors. Each of the capacitors of the second CDAC includes a top plate coupled to a second input of the comparator, and a bottom plate switchably coupled to a ground reference.

Abstract: A method for non-linearity correction includes receiving a first output signal from a data signal path containing a first analog-to-digital converter and receiving a second output signal from a second analog-to-digital converter. The method also includes generating first non-linearity coefficients using the first output signal and generating second non-linearity coefficients using the first and second output signals. The method further includes applying, by a non-linearity corrector in the data signal path, the first and second non-linearity coefficients to compensate for non-linearity components in a digitized signal output from the first analog-to-digital converter to generate a corrected digitized signal.

Abstract: A supply-to-digital regulation loop (SDRL) circuit, including a reference supply circuit and a local supply circuit. The reference supply circuit includes a reference supply-to-digital converter (SDC) to convert an analog reference supply voltage to a digital reference signal. The local supply circuit is coupled to the reference supply circuit. The local supply circuit includes a local SDC to convert an analog local supply voltage to a digital local supply signal based on a digital feedback signal, and a local monitoring circuit to monitor the digital feedback signal based on a comparison of the digital local supply signal with the digital reference signal routed from the reference SDC of the reference supply circuit.

Abstract: The present application discloses a data converter (112). The data converter includes an input terminus (98), a digital-to-analog (D/A) converter (116) and a mapping unit (114). The input terminus is configured to receive an input signal. The D/A converter includes a plurality of D/A converter units configured to generate an output signal. The mapping unit is coupled between the input terminus and the D/A converter and is configured to cause the plurality of D/A conversion units to be equivalently arranged in a relative order in which the plurality of D/A conversion units are gated according to specific electrical characteristics of the plurality of D/A conversion units for digital-to-analog conversion. The present application further provides an A/D converter, a D/A converter and a related chip.

Abstract: An end-fire antenna for wideband low form factor applications includes a first metal layer, a second metal layer, and a dielectric layer disposed between the first and second metal layers. An open cavity formed in the dielectric layer that is filled with air, the cavity defined by a pair of sidewalls that extend from an aperture of the cavity to a rear wall of the cavity, where the depth of the aperture is defined between the aperture and the rear wall. The cavity is formed by selecting the width of the aperture of the cavity and the depth of the cavity such that the antenna achieves the same gain during operation irrespective of a variation in the thickness of the antenna.

Abstract: A system has a digital-to-analog converter; a reference signal coupled to the digital-to-analog converter; a differential amplifier for applying gain, and for generating output signals as a function of sampled input signals, the reference signal, digital codes, and the gain applied by the differential amplifier coupled to the digital-to-analog converter; and a multi-bit successive-approximation register for determining the digital codes in successive stages coupled to the differential amplifier; and the gain applied by the differential amplifier is corrected based on previously determined digital codes.

Abstract: A base station antenna that extends along a first longitudinal axis includes a first array configured to emit electromagnetic radiation. The first array includes a first column of radiating elements, the first column including a first radiating element and a pair of second radiating elements. The first radiating element is a cross dipole radiating element and the pair of second radiating elements includes a pair of second radiating elements that are disposed facing each other on both sides of the first longitudinal axis, where each of the second radiating elements includes first and second radiating arms that extend respectively in opposite directions substantially along the first longitudinal axis, and a third radiating arm that extends toward the first longitudinal axis substantially perpendicular to the first and second radiating arms.

Abstract: The present invention relates to an antenna assembly for a beamforming antenna, comprising a reflector and an antenna array that includes a plurality of first radiating elements that are arranged as a first vertically extending array, the first radiating elements extending forwardly from the reflector; and a plurality of second radiating elements that are arranged as a second vertically extending array, the second radiating elements extending forwardly from the reflector. Two adjacent first radiating elements are spaced apart from one another by a first distance, and a first radiating element and an adjacent second radiating element are spaced apart from one another by a second distance. The first distance is substantially equal to the second distance. The antenna assembly further comprises a plurality of parasitic elements that are placed along sides of the first and second of the vertically extending arrays.

Abstract: A support member for arrangement with additional support members to form an array of dipole antennas. The support member includes a first portion of a conductive arm of a dipole antenna, and a first portion of a conductive arm of another dipole antenna. A second portion of the conductive arm of the dipole antenna extends from the first portion of the conductive arm of the dipole antenna towards the first portion of the conductive arm of the other dipole antenna, defining a gap in a direct current path between the second portion of the conductive arm of the dipole antenna and the first portion of the conductive arm of the other dipole antenna.

Abstract: A hearing assistance device comprising a housing component (12) containing a transceiver (68) and processing circuitry arranged in a compact block structure (50), an antenna feed element electrically connected to the transceiver (68), and an antenna element (30, 80) mounted integral with the housing component (12). The antenna feed element is mounted on the compact block structure (50), and is electromagnetically coupled to the antenna element (30, 80).

Abstract: A system and method for suppressing aperture noise resulting from clock jitter associated with a Nyquist analog-to-digital converter (ADC) using self-referred time measurements are provided. The system comprises of a clock, a delay element, a time subtractor, a time-to-digital converter, a filter element, a first digital subtractor, an integrator, a differentiator, and a multiplier. Each of the delay element, time subtractor, time-to-digital converter, filter element, first digital subtractor, integrator, and multiplier is electrically connected in parallel with the ADC, which allows the clock to generate a clock signal that advances into the system and the ADC in order to isolate and suppress the noise aperture associated with the ADC. As such, the architecture of the system is configured to isolate and suppress aperture noise resulting from clock jitter associated with an analog-to-digital converter (ADC) to allow the output signal of the system be independent of the aperture noise.

Abstract: A data compressor includes a zero-value remover, a zero bit mask generator and a non-zero values packer. The zero-value remover receives 2N bit streams of values and outputs 2N non-zero-value bit streams having zero values removed from each respective bit stream based on a selected granularity of compression for values contained in the bit streams. The zero bit mask generator receives the 2N bit streams of values and generates a zero bit mask corresponding to the selected granularity of compression. Each zero bit mask indicates a location of a zero value based on the selected granularity of compression. The non-zero values packer receives the 2N non-zero-value bit streams and forms at least one first group of packed non-zero values.

Abstract: A high-frequency module (1) includes a multilayer dielectric substrate (2), an RFIC (21), and an array antenna (13). The array antenna (13) includes a plurality of first patch antennas (11) having identical polarization directions with each other, and a plurality of second patch antennas (12) having identical polarization directions with each other, which are polarization directions positioned between two orthogonal polarizations of the first patch antenna (11). The first patch antenna (11) and the second patch antenna (12) simultaneously operate as a transmitting antenna or a receiving antenna.

Abstract: The present disclosure provides a dual-polarized radiating element comprising a feeding arrangement and four dipole arms. The feeding arrangement comprises four slots, which extend from a periphery towards a center of the feeding arrangement and are arranged at regular angular intervals forming a first angular arrangement. The four dipole arms extend outwards from the feeding arrangement and are arranged at regular angular intervals forming a second angular arrangement. The second angular arrangement of the four dipole arms is rotated with respect to the first angular arrangement of the four slots.