Abstract: An array antenna is provided with: a first conductive member including a planar part; plural antennas arranged at a predetermined first interval to the planar part of the first conductive member, each of the plural antennas transmitting and receiving radio frequencies of a first polarization and radio frequencies of a second polarization that is different from the first polarization; and a second conductive member provided between the antennas adjacent to each other among the plural antennas via a gap of a predetermined second interval to the planar part of the first conductive member, the second conductive member being capacitively coupled to the first conductive member.

Abstract: Various embodiments of the present technology may provide methods and apparatus for a successive approximation register analog-to-digital converter (SAR ADC). The SAR ADC may provide a first digital calibration circuit configured to correct systemic mismatch and a second digital calibration circuit configured to correct random mismatch. Together, the first and second digital calibration circuits resolve missing codes in the SAR ADC output.

Abstract: A system includes an analog-to-digital converter (ADC) and a digital modulator coupled to the ADC, wherein the digital modulator comprises an output for providing a digital signal, wherein the digital modulator comprises a main signal path and a feedback path, and wherein the feedback path comprises a first digital gain stage having a first adjustable gain range.

Abstract: The present disclosure provides a spatial feeding end-fire array antenna based on electromagnetic surface technologies, including: a primary feed, configured to transmit and/or receive electromagnetic waves; and a single-layer and/or multi-layer medium-metal combination surface, configured to convert the electromagnetic waves emitted from the primary feed to an end-fire focused beam, or to concentrate space waves received in an end-fire direction into the primary feed. The single-layer and/or multi-layer medium-metal combination surface has a thickness that is equal to or less than one percent of working wavelength of the antenna.

Abstract: A delta-sigma modulator generates a bit stream signal from an analog signal by operating according to a modulation period including a sampling period and a filtering period and includes a digital-to-analog converter (DAC) configured to generate a charge signal according to one of a first reference voltage and a second reference voltage according to the bit stream signal during the sampling period and to output a signal generated according to the charge signal and the other of the first reference voltage and the second reference voltage; a loop filter configured to charge a sampling signal corresponding to the analog signal during the sampling period and to filter an output from the DAC and a signal generated according to the sampling signal during the filtering period; and a quantizer configured to generate the bit stream signal according to an output from the loop filter in the modulation period.

Abstract: An antenna device includes: a dielectric substrate 1; a first conductor 2 provided on a first surface of the dielectric substrate 1; a second conductor 100 provided on a second surface of the dielectric substrate 1, the second surface being opposite to the first surface on which the first conductor 2 is provided, the second conductor 100 having a feeding point 12; a third conductor 200a provided on the same second surface on which the second conductor 100 is provided; and a pair of transmission lines that electrically connect the second conductor 100 and the third conductor 200a.

Abstract: A charge sharing circuit includes a charge source having an accumulated first charge and a charge load having an accumulated second charge, where during a charge sharing interval the second charge is less than the first charge. A charge sharing regulator selectively couples between the charge source and the charge load along a charge sharing path. The charge sharing regulator regulates transfer of a shared amount of charge from the charge source to the charge load during the charge sharing interval.

Abstract: An antenna structure includes a ground element, a feeding radiation element, a first radiation element, a second radiation element, a third radiation element, and a switch circuit. The ground element provides a ground voltage. The feeding radiation element has a feeding point. The feeding radiation element is coupled through the first radiation element to the second radiation element. The third radiation element is coupled to the feeding radiation element. The feeding radiation element is disposed between the first radiation element and the third radiation element. The switch circuit selectively couples the second radiation element to the ground voltage according to a control voltage. A slot is formed and surrounded by the ground element, the feeding radiation element, the first radiation element, and the second radiation element.

Abstract: An antenna includes a radiator, where the radiator includes three parts separated by a gap, an end of a second part proximate to a first part is a first end, and an end of the second part proximate to a third part is a second end, a medium-high frequency feeder, electrically coupled to the radiator at a first coupling point, a low frequency feeder electrically coupled to the radiator, a first ground cable electrically coupled to the radiator at a second coupling point, where an adjustable component for controlling conduction of the first ground cable is disposed on the first ground cable, a length from the second coupling point to an end that is in the first end and the second end and that is further from the first coupling point is a quarter of a wavelength corresponding to a resonance frequency.

Abstract: A delta-sigma modulator includes a first integrator and a comparator. The comparator's positive input couples to the first integrator's positive output, and the comparator's negative input couples to the first integrator's negative output. A first current DAC comprises a current source device, and first and second transistors. The first transistor has a first transistor control input and first and second current terminals. The first current terminal couples to the current source device, and the second current terminal couples to the first integrator positive output. The second transistor has a second transistor control input and third and fourth current terminals. The third current terminal couples to the current source device, and the fourth current terminal couples to the first integrator negative output. A first capacitive device couples to the second transistor control input and to both the second current terminal and the first integrator positive output.

Abstract: The invention concerns an antenna, comprising at least two non-ferrous metal plates, at least one first plate forming a radiating portion and a second plate forming a mass plane, at least one substrate, arranged between the mass plane and the radiating portion, and an excitor of length at least equal to the thickness of the substrate, extending between the mass plane and the radiating portion and connected to the radiating portion, and adapted to supply the antenna, characterised in that the substrate is a dispersive ferromagnetic substrate, called dispersive ferrite presenting, as magnetic features, a high relative magnetic permeability comprised between 10 and 10,000 and a high magnetic loss tangent greater than 0.1, said antenna comprising means for gradually and locally reducing magnetic features of the dispersive ferrite.

Abstract: A method for testing an A/D converter with a built-in diagnostic circuit with a user supplied variable input voltage includes generating a charge by a binary-weighted capacitor array responsive to an external voltage and a user specified code. The method further includes applying the charge to a first input of a voltage comparator and applying a bias voltage to a second input of the voltage comparator, and generating, by the voltage comparator, a comparison voltage responsive to the applied charge and the bias voltage. The method also includes applying the comparison voltage to an input of a successive approximation register and generating, by the successive approximation register, an approximate digital code responsive to the comparison voltage. The method also includes determining if at least one bit of the approximate digital code fails to toggle independent of adjacent bits.

Abstract: An electronic device that includes an antenna structure installable in a narrow space is provided. The electronic device may include a first support member, a second support member, a printed circuit board (PCB), an antenna, and a first connector. The second support member is disposed in parallel with the first support member such that a lower surface thereof faces the first support member, and combined with the first support member through a plurality of fixing members. The PCB is disposed between the first and second support members and fixed by the plurality of fixing members. The antenna includes a flexible printed circuit board (FPCB), a short range communication antenna pattern formed on the FPCB, and a wireless charging coil formed on the FPCB.

Abstract: An antenna structure includes a substrate, a first polarization antenna group, and a second polarization antenna group. The substrate is defined with a first axis and a second axis. The first polarization antenna group and the second polarization antenna group are disposed on the substrate. The first polarization antenna group includes a first dipole antenna, a second dipole antenna, and a first wire. The first wire is separate from and coupled to the first dipole antenna and the second dipole antenna. The second polarization antenna group includes a third dipole antenna, a fourth dipole antenna, and a second wire. The second wire is separate from and coupled to the third dipole antenna and the fourth dipole antenna.

Abstract: Certain aspects provide a circuit for analog-to-digital conversion. The circuit generally includes a flash analog-to-digital converter (ADC) having a plurality of comparators, each comparator being configured to compare an input voltage to a reference voltage; and a calibration circuit coupled to the flash ADC and configured to tune the reference voltage prior to a conversion operation by the flash ADC.

Abstract: Quantisation methods are provided which employ dither techniques to reduce the noise penalty in certain circumstances whilst still removing noise modulation. One method relates to reducing the wordwidth of audio by one bit, while another method relates to burying one bit of data in a pair of signal samples.

Abstract: The present disclosure relates to a time-interleaved ADC circuit. The time-interleaved ADC circuit comprises an input for an analog input signal, a first ADC bank comprising a first plurality of parallel time-multiplexed ADCs, wherein the first plurality of parallel time-multiplexed ADCs is configured to subsequently generate a first plurality of samples of the analog input signal during a first time interval, a first buffer amplifier coupled between the input and the first ADC bank. The time-interleaved ADC circuit further comprises a second ADC bank comprising a second plurality of parallel time-multiplexed ADCs, wherein the second plurality of parallel time-multiplexed ADCs is configured to subsequently generate a second plurality of samples of the analog input signal during a second time interval, wherein the first and the second time intervals are subsequent time intervals, a second buffer amplifier coupled between the input and the second ADC bank.

Abstract: In an example, a circuit includes a first comparator, a second comparator, a pulse counter, a processor, a first ADC, and a second ADC. The first comparator has a first input coupled to a first node, a second input, and an output. The second comparator has a first input coupled to a second node, a second input, and an output. A first DAC is coupled to the second input of the first comparator. A second DAC is coupled to the second input of the second comparator. The pulse counter has a first input coupled to the output of the first comparator and a second input coupled to the output of the second comparator. The first ADC has an input coupled to the first node and an output coupled to the processor. The second ADC has an input coupled to the second node and an output coupled to the processor.

Abstract: A method of fabricating a monolithic feedboard assembly for a base station antenna, the method comprises injection molding a unitary frame that includes a feedboard section and at least one radiating element section and then selectively depositing metal on the unitary frame to form radio frequency transmission lines and radiators on the unitary frame to provide the monolithic feedboard assembly.

Abstract: A liquid crystal alignment agent according to the present invention includes: an alignment film forming material; and an organic solvent. The organic solvent contains a compound which has at least two functional groups selected from the group consisting of a methylene group, a methyl group, an ether group, a ketone group, and a hydroxyl group, and does not contain a nitrogen atom.