Abstract: An antenna includes an antenna substrate comprising a first end and a second end, and an antenna element attached to the antenna substrate. The antenna element is configured to receive communication signals within a partial hemispherical-shaped signal reception region oriented about the first end of the antenna substrate. A signal gain reduction portion is at least partially located between the antenna element and the second end of the antenna substrate, and is configured to reduce signal gain in an opposite partial hemispherical-shaped region oriented about the second end of the antenna substrate.

Abstract: A decoding device is used to securely send corresponding data gathered from multiple underground sources to multiple users. The device comprises a signal receiving port connected to multiple bandwidth filters and further connected to internet access points that are assigned to end users for secure data access. The invention facilitates allowing the signal and data being transmitted through the formation of the earth to reach end users located nearby and significant distances away from the source of the transmission. A system and method utilizing the decoding device is provided.

Abstract: An instrument configured to process signal data is disclosed. The instrument is operable to control and or change the sampling rate of the signal data from a first sample rate to a second sample rate different than the first sample rate.

Abstract: A circuit includes a transconductance stage having first and second outputs. The circuit also includes a comparator having first and second inputs. The first input is coupled to the first output, and the second input is coupled to the second output. The comparator includes first through fifth transistors and a pair of cross-coupled transistors. The pair of cross-coupled transistors is coupled to the second current terminals of the first and second transistors. The second current terminal of the third transistor is coupled to the second current terminal of the first transistor, and the first current terminals of the first, second, and third transistors are coupled together. The second current terminals of the fourth and fifth transistors are coupled together and to the control input of the third transistor.

Abstract: The present technology relates to a signal processing apparatus, a signal processing method, and a program that allow an improvement in the rate of modulation of PWM signals. Pulse width modulation (PWM) is performed to convert one of a 0 or 1 represented by a bit of a pulse density modulation (PDM) signal into which an audio signal has been PDM-modulated, into a maximum-length pulse of a maximum pulse width of a PWM signal having a period equal to the period of the PDM signal, and convert the other of the 0 or 1 of the PDM signal into a minimum-length pulse of a minimum pulse width of the PWM signal at a position adjacent to the center of the period of the PWM signal. The present technology is applicable, for example, to audio reproduction systems that reproduce audio signals.

Abstract: A delta-sigma modulator (DSM) with non-recursive computation of delta-sigma residues comprising: an input port for receiving a digital input signal; a residue calculation circuit coupled to the input port for calculating delta-sigma residues non-recursively; a DSM output calculation circuit coupled to the output of the residue calculation circuit for generating an output of the DSM; and a second input port for receiving a control signal, wherein the control signal dynamically adjusts an output frequency band of the DSM.

Abstract: Techniques for improving a power supply accuracy of a precision data converter system, such as analog-to-digital converter circuits (ADCs) and digital-to-analog converter circuits (DACs). Improving the power supply accuracy can enable a reference voltage to be as large as possible, thereby increasing the signal-to-noise-ratio (SNR). The techniques can also simplify power supply sequencing requirements for the data converter system.

Abstract: A communication device includes a nonconductive housing, a cable, an antenna structure, and a signal source. The nonconductive housing has a hollow structure. The cable is coupled to the signal source. The cable includes a signaling conductor and a grounding conductor. The antenna structure includes an antenna body and an enclosed radiation element. The antenna body is coupled to the signaling conductor. The antenna body is disposed outside the nonconductive housing. The enclosed radiation element is coupled to the grounding conductor. The enclosed radiation element is disposed inside the nonconductive housing.

Abstract: Described herein is an improved apparatus for increasing the performance of a ?? modulator, which may function as an ADC. In one embodiment, the ?? modulator comprises a voltage to current converter, a capacitor connected between two outputs of the voltage to current converter to receive a differential input current, and a switch that can switch between connecting each output of the voltage to current converter to ground while disconnecting the other output of the voltage to current converter. In this embodiment, the ?? modulator has no common mode control loop, and no reference current. This results in decreased complexity, i.e., fewer components, as well as reduced noise.

Abstract: A digital filter and a method for filtering a pulse density modulation (PDM) signal are presented. The digital filter has a first filter circuit to receive an input signal with input values at successive time steps to provide a filtered input signal with filtered values at successive time steps. The digital filter does not require sample-rate or data format conversions. Also, the digital filter is area and power efficient when implemented in hardware. Optionally, the digital filter has a sigma-delta modulator including the quantiser, the sigma-delta modulator being used to receive the filtered input signal and to process the filtered input signal before and/or after being quantised by the quantiser. This digital filter does not require sample-rate or data format conversions. This digital filter is area and power efficient when implemented in hardware.

Abstract: A broadband digitizer for an applied broadband analog input signal SA(t). The digitizer includes a low frequency analog-to-digital converter (LF ADC) channel and a high frequency analog-to-digital converter (HF ADC) channel, an input splitter coupled to respective inputs to the LF ADC channel HF ADC channels, a frequency divider, and a combining unit. Low frequency portions of SA(t) are digitized to digital signal SDLF[n] in the LF ADC channel and high frequency portions of SA(t) are digitized to digital signal SDHF[n] in the HF ADC channel. The combining unit combines the digital signals SDLF[n] and SDHF[n] to form distortion-reduced SD[n], corresponding to SA(t). Front ends of the LF ADC channel and HF ADC channel reduce level-caused distortions, and the combining unit reduces ADC frequency-caused, time-position-caused, and interpolation-caused distortions.

Abstract: Described herein are apparatus and methods for low speed characterization of a high-speed signal. A circuit includes a sub-sampling circuit configured to sub-sample a high-speed signal received from a device, a reconstruction loop circuit configured to reconstruct a low-speed signal from the sub-sampled high-speed signal, a low pass filter configured to filter the reconstructed low-speed signal, a discrete time low pass filter configured to mitigate skew rate requirements of the filtered low-speed signal for a digitization circuit, a continuous time low pass filter configured to smooth the skew rate mitigated low-speed signal and the digitization circuit is configured to generate a digital representation of the smoothed low-speed signal for characterization by a characterization device, and shape a noise associated with the smoothed low-speed signal outside a frequency range of interest of the smoothed low-speed signal.

Abstract: A sigma-delta analog-to-digital converter (ADC) is disclosed. The sigma delta ADC has an analog input and a digital output. A sigma-delta modulator input is coupled to the analog input and a sigma-delta modulator output. A first filter having a first filter input is coupled to the sigma-delta modulator output and a first filter output. A second filter having a second filter input is coupled to the sigma-delta modulator output and a second filter output. The sigma-delta ADC operates in a first and second mode. In a first mode, the first filter output is coupled to the digital output. In a second mode, the second filter output is coupled to the digital output.

Abstract: Method for encoding of quality values of a data structure, whereby said data structure comprises a set of genomic reads, wherein the method comprises the following steps executable by a data processing system: ascertain the quality values of each read covering a certain index locus, —determine a codebook identifier identifying a specific codebook from a plurality of codebooks for said certain index locus based on the ascertained quality values of said certain index locus, whereby each code-book provides a mapping from a quality value of said quality value alphabet to a corresponding quantized quality value of a quantized quality value alphabet, —quantizing all ascertained quality values at said certain index locus using the specific codebook identified by the codebook identifier at said certain index locus in order to obtain for each quality value at said certain index locus a corresponding quantized quality value, and —encode all determined codebook identifiers using a first entropy encoder and encode all qu

Abstract: A data serialization circuit includes a clock data operation circuit configured to generate a plurality of delay clock signals and a plurality of synchronous data signals in response to a plurality of parallel data signals and a plurality of multi-phase clock signals and a multiplexer configured to output a serial data signal in response to the plurality of delay clock signals and the plurality of synchronous data signals. A first one of the plurality of delay clock signals substantially aligns with a first one of the plurality of synchronous data signals.

Abstract: Described are apparatus and methods for successive approximation register (SAR) analog to digital converter (ADC) (SAR ADC) with factoring and background clock calibration. An apparatus includes a SAR ADC configured to, in response to receiving an enable flag based on detection of an acquisition clock with a first logic state sent by a controller, sample and convert a pair of differential input signals using a sampling clock to obtain a defined number of samples in an acquisition clock cycle and a factoring circuit configured to obtain the defined number of samples from the SAR ADC using a capturing clock based on the sampling clock, factor the defined number of samples, and send a factored samples ready flag to the controller.

Abstract: There is provided an analog signal gauge that monitors an analog signal at a node and a non-volatile memory element to store an event that occurs at the node when a certain criteria, such as exceeding a maximum safe threshold, is satisfied. This way, the analog signal gauge can help to provide an accurate picture of the operating characteristics in the analog circuit which it is monitoring, including indications of faults that occur in the analog system.

Abstract: A clock-less delay comparator coupled to a first input signal and a second input signal, the clock-less delay comparator comprising: a first transistor having a control terminal coupled to the second input signal, a first current terminal coupled to a first voltage supply, and a second current terminal; a second transistor having a control terminal, a first current terminal coupled to the first voltage supply, and a second current terminal; a third transistor having a control terminal, a first current terminal coupled to the first voltage supply, and a second current terminal; a fourth transistor having a control terminal coupled to the first input signal, a first current terminal coupled to the first voltage supply, and a second current terminal; a fifth transistor having a control terminal coupled to the second input signal, a first current terminal, and a second current terminal coupled to the control terminal of the third transistor; a sixth transistor having a control terminal coupled to the first input

Abstract: Systems, apparatuses, and methods related to bit string compression are described. A method for bit string compression can include determining that a particular operation is to be performed using a bit string formatted according to a universal number format or a posit format to alter a bit width associated with the bit string from a first bit width to a second bit width and performing a compression operation on a bit string formatted according to a universal number format or a posit format to alter a bit width associated with the bit string from a first bit width to a second bit width. The method can further include writing the bit string having the second bit width to a first register, performing an arithmetic operation or a logical operation, or both using the bit string having the second bit string width, and monitoring a quantity of bits of a result of the operation.

Abstract: Disclosed herein are related to systems and methods for a power efficient successive approximation analog to digital converter (SAR ADC). In one aspect, the SAR ADC includes a sample and digital to analog conversion (DAC) circuit to sample an input voltage. In one aspect, the SAR ADC includes a first comparator coupled to the DAC circuit, and a first set of storage circuits coupled between the first comparator and the DAC circuit. In one aspect, the SAR ADC includes a second comparator coupled to the DAC circuit, and a second set of storage circuits coupled between the second comparator and the DAC circuit. In one aspect, the SAR ADC includes a control circuit configured to select, for each of multiple bits corresponding to the input voltage, a corresponding comparator to determine a state of the each of the multiple bits during a corresponding time period.