Abstract: An antenna array includes a plurality of antenna elements disposed on the same plane. The antenna elements are arranged to form a symmetrical pattern. The symmetrical pattern is neither square nor rectangular. The antenna elements have the same output power. The radiation pattern of the antenna array includes a main lobe and a side lobe. The main lobe is higher than the side lobe by at least 18 dB.

Abstract: A sampling device comprises a clock source that provides a clock frequency, a converter with a receiving port for receiving the clock frequency, and a re-sampler located in a digital domain of the sampling device. The clock source is configured to vary the clock frequency over time. The clock source is configured to forward the clock frequency to the converter in order to change a sampling rate of the converter in dependency of the clock frequency. An output sample rate of the sampling device is fixed.

Abstract: A dual-band antenna is provided. The dual-band antenna includes a first antenna, a second antenna, and a grounding component. The first antenna has a first feed point for transceiving a first signal. The second antenna has a second feed point. The grounding component is electrically coupled to the first feed point and the second feed point, wherein the grounding component forms a first path and a second path between the first feed point and the second feed point, wherein a first path length of the first path and a second path length of the second path are integer multiples of a first wavelength of the first signal.

Abstract: Signal quality is improved in a circuit for amplifying and sampling an analog signal. An input signal is input to one end of an input-side resistor. An operational amplifier amplifies the input signal, and outputs the input signal from an output terminal as an amplified signal. One end of a filter capacitor is connected to an input terminal of the operational amplifier. A predetermined frequency component of the input signal passes through the filter capacitor. A sampling capacitor imports the amplified signal during a predetermined sampling period, and holds the amplified signal during a predetermined hold period. A sampling switch connects the output terminal of the operational amplifier to one end of the sampling capacitor during the sampling period, and disconnects the output terminal of the operational amplifier from one end of the sampling capacitor during the hold period.

Abstract: A ring oscillator-based analog-to-digital converter (ADC). The ring oscillator-based ADC includes a ring oscillator and a transition detector. The ring oscillator may include a set of inverters coupled in a ring wherein an output of an inverter is coupled to an input of a successive inverter in the ring. The transition detector is configured to detect transitions of outputs of the inverters by comparing outputs of two separate inverters at two consecutive time instances. The transition detector may include two sets of registers configured to store outputs of the set of inverters at two consecutive time instances, respectively, and a set of comparators configured to compare the outputs stored in the two sets of registers. Each comparator may be configured to compare an output of one inverter at a first time instance and an output of another inverter at a second time instance.

Abstract: A system includes a multiplying digital-to-analog converter (MDAC). The system also includes an input-side component coupled to the MDAC and configured to provide a code to the MDAC. The system also includes a reference voltage source coupled to the MDAC and configured to provide a reference voltage to the MDAC. The MDAC comprises a nonlinear calibration circuit configured to adjust an output of the MDAC nonlinearly based on the code, the reference voltage, and an output of the nonlinear calibration circuit.

Abstract: An encoding and decoding method for an optical isolation amplifier including an encoder, an optical driver, a light source, an optical detector, and a decoder, and employing sigma-delta modulation technology is provided. The method includes: generating a plurality of first pulses, each having a predetermined pulse width, through the encoder when an input digital signal experiences an input pulse rising or falling edge; outputting an encoded signal having the plurality of first pulses to the optical driver; driving the light source through the optical driver, according to the plurality of first pulses, so as to output an encoded optical signal; generating a detected signal through the optical detector detecting the encoded optical signal, and the detected signal has a plurality of second pulses; and duplicating the input digital signal of the encoder through the decoder, according to the detected signal having the plurality of second pulses.

Abstract: Various embodiments include methods and devices for implementing compression of high dynamic ratio fields. Various embodiments may include receiving a compression block having data units, receiving a mapping for the compression block, wherein the mapping is configured to map bits of each data unit to two or more data fields to generate a first set of data fields and a second set of data fields, compressing the first set of data fields together to generate a compressed first set of data fields, and compressing the second set of data fields together to generate a compressed second set of data fields.

Abstract: An analog-to-digital converter includes a comparator configured to compare an input signal with a reference signal and to output a comparison signal indicating a corresponding comparison result, a control logic configured to output a control signal for adjusting the reference signal based on the comparison signal, and a reference signal adjusting circuit configured to adjust the reference signal based on the control signal. The comparator includes a first pre-amplifier configured to amplify a difference between the input signal and the reference signal using a first transistor having a first size, a second pre-amplifier configured to amplify the difference between the input signal and the reference signal using a second transistor having a second size different from the first size, and a latch configured to generate the comparison signal using at least one of an output of the first and second pre-amplifiers. The first and second pre-amplifiers share the latch.

Abstract: Disclosed is a telecommunications antenna having a plurality of cloaked low band (LB) and high band (HB) dipoles. The LB and HB dipoles provide cloaking by breaking the dipoles into dipole segments, and providing conductive cloaking elements over the gaps between dipole segments to form a plurality of capacitors along the dipole. The capacitors along the LB dipoles provide a low impedance to LB RF signals and a high impedance to HB signals. The capacitors formed on the HB dipoles provide a low impedance to RF signals and high impedance to harmonics of the LB RF signals. This cross-cloaking of dipoles enables more dense arrangements of LB and HB dipoles on an antenna array face, providing opportunities to arrange, for example, the LB dipoles with an array factor that results in an advantageous fast roll off gain pattern.

Abstract: Techniques for testing circuits, such as converter circuits, such as digital-to-analog converter circuits (DACs), are described. A digital signal processor (DSP) can generate a waveform, such as sine wave, and apply the sine wave to the circuit under test, e.g., a DAC. The DAC can generate an output and the DSP can regenerate the waveform and determine an accuracy of the DAC such as to determine whether the DAC meets one or more specified criteria. In some example implementations, the tests can be performed using variable voltage amplitude segments.

Abstract: A method for calibrating a successive-approximation analog-to-digital converter (ADC) includes configuring the successive-approximation ADC in a calibration mode of operation. The method includes, while in the calibration mode of operation: determining a digital code corresponding to a programmable capacitance of the successive-approximation analog-to-digital converter, and storing the digital code corresponding to the programmable capacitance in a storage element of an integrated circuit die including the successive-approximation ADC. The programmable capacitance may be a gain tuning capacitance, a bridge tuning capacitance, an offset capacitance, or a monotonicity tuning capacitance.

Abstract: An antenna system includes a dielectric substrate, a first dipole antenna element, a second dipole antenna element, a first additional metal element, a second additional metal element, first conductive via elements, and second conductive via elements. The first dipole antenna element and the first additional metal element are disposed on a first surface of the dielectric substrate. The first dipole antenna element includes a first radiation element and a second radiation element. The second dipole antenna element and the second additional metal element are disposed on a second surface of the dielectric substrate. The second dipole antenna element includes a third radiation element and a fourth radiation element. The first additional metal element is coupled through the first conductive via elements to the third radiation element. The second additional metal element is coupled through the second conductive via elements to the first radiation element.

Abstract: A DAC driver includes a number of DAC drivers coupled to a load network. A first DAC driver includes a first set of data switches that can be controlled by a first digital input signal. The first DAC driver further includes a first set of output switches, a first set of dump switches and a first set of current sources. Another DAC driver includes a second set of output switches, dump switches, and current sources. The first set of output switches or the second set of output switches are operable to respectively couple either one of the first set of data switches or the first set of current sources to the load network. The first set of dump switches or the second set of dump switches are operable to respectively dump the first set of current sources or the second set current sources into a respective dump load.

Abstract: An antenna array includes a dielectric substrate, a ground metal plane, a first antenna unit, a second antenna unit, a third antenna unit, and a fourth antenna unit. The first antenna unit includes a first metal loop and a first feeding metal element. The first feeding metal element is adjacent to the first metal loop. The second antenna unit includes a second metal loop and a second feeding metal element. The second feeding metal element is adjacent to the second metal loop. The third antenna unit includes a third metal loop and a third feeding metal element. The third feeding metal element is adjacent to the third metal loop. The fourth antenna unit includes a fourth metal loop and a fourth feeding metal element. The fourth feeding metal element is adjacent to the fourth metal loop.

Abstract: Buried object locators including an omnidirectional antenna array and a gradient antenna array are disclosed. A locator display may include information associated with a buried object determined based on processing of both omnidirectional antenna array signals and gradient antenna array signals.

Abstract: A ultra-high speed DAC apparatus (e.g., with a full sampling frequency not less than 20 GHz) may include one or more digital pre-coders and DAC modules. Each DAC module may include multiple current-mode DAC systems and a first power combiner. The gate length of transistors within each DAC module may be between 6 and 40 nm. Each current-mode DAC system includes a transmission line (e.g., 40 to 80 microns long) coupled to multiple interleaving sub-DAC systems (within the current-mode DAC systems) and the first power combiner. The first power combiner combines, without interleaving, analog signals that have been interleaved within the current-mode DAC systems. The impedance of the first power combiner matches the impedance of each of the current-mode DAC systems and a load of the first power combiner. A second power combiner combines, without interleaving, analog signals from the DAC modules.

Abstract: An antenna includes an antenna substrate comprising a first end and a second end, and an antenna element attached to the antenna substrate. The antenna element is configured to receive communication signals within a partial hemispherical-shaped signal reception region oriented about the first end of the antenna substrate. A signal gain reduction portion is at least partially located between the antenna element and the second end of the antenna substrate, and is configured to reduce signal gain in an opposite partial hemispherical-shaped region oriented about the second end of the antenna substrate.

Abstract: A decoding device is used to securely send corresponding data gathered from multiple underground sources to multiple users. The device comprises a signal receiving port connected to multiple bandwidth filters and further connected to internet access points that are assigned to end users for secure data access. The invention facilitates allowing the signal and data being transmitted through the formation of the earth to reach end users located nearby and significant distances away from the source of the transmission. A system and method utilizing the decoding device is provided.

Abstract: An instrument configured to process signal data is disclosed. The instrument is operable to control and or change the sampling rate of the signal data from a first sample rate to a second sample rate different than the first sample rate.