Abstract: A memory access control circuit determines an optimum memory access mode and performs the optimum memory access mode without requiring additional data from the data processing unit. The circuit performs a plurality of memory access operations, the number of which is larger than the number of access modes designated by the data processing unit, and decides automatically which memory access is to be performed, and independently executes the appropriate memory access. The memory access control circuit provides memory access control functions which make it particularly suited for use in a graphics display system.

Abstract: A stable memory circuit which includes a pair of memory banks (2(a)) and (2(b)) each having eight arrays of eight VRAMs (3). Each VRAM (3) is dual-ported and includes a processor port connected to a processor bus (6) and a stable memory port connected to a stable memory bus (7). Accordingly, stable memory operations such as copying operations may be carried out on the stable memory bus (7) concurrently with conventional random accesses by a host processor via the processor port (6) and with very little use of processor time. Further, the stable memory ports of VRAMs (3) are serial ports and each memory bank (2(a)) and (2(b)) may transfer data at high speed using wide serial data path.

Abstract: A virtual memory system groups pages into clusters according to use, determined by first reference and frequency of reference. The virtual memory system comprises a random access memory and an auxiliary memory. A central processing unit the virtual memory system with an address. Whenever that address identifies a memory location not stored in the RAM, the entire cluster of pages in which the address is located is retrieved from the auxiliary memory into the random access memory.

Abstract: The disk drive array data storage subsystem maps between virtual and physical data storage devices and schedules the writing of data to these devices. The data storage subsystem functions as a conventional large form factor disk drive memory, using a plurality of redundancy groups, each containing N+M disk drives. A performance improvement is obtained by eliminating the disk formatting delays found in the prior art. In order to accommodate the need to format virtual volumes to be compatible with the form and format of the data records to be transmitted by the host processor, the present disk drive array memory system stores format information in a virtual track directory which controls the mapping of the virtual cylinders defined by the host processor into the physical elements of the disk drive array.

Abstract: A memory selection circuit of a computer provided with a central processing unit and a plurality of memory areas of an equal capacity, including the first circuit for storing data corresponding to the capacity of the plurality of memory areas outputted from the central processing unit, the second circuit for storing an address outputted from the central processing unit, the third circuit for generating a signal that indicates a difference between the address stored in the second circuit and a predetermined address assigned to a beginning of the plurality of memory areas; and the fourth circuit for generating a selection signal for selecting one of the plurality of memory areas on the basis of the data stored in the first circuit and the signal generated by the third circuit.

Abstract: In a CD-ROM disk reproducing device, for a data read instruction which specifies an address issued frequently from a host computer, irrespective of whether the device has a Lock Cache function, the time required from receipt of a data read instruction up to the actual data transfer is reduced. The data read instruction which specifies an address issued frequently from the host computer is discriminated by a microcomputer constituting a control section in the device and the read data from the address is locked in a storage section (buffer RAM) so as not to be erased. When a data read instruction specifying the same address is received afterward, data is read out directly from the storage section and transferred to the host computer.

Abstract: A processing apparatus of an integrated circuit structure for a multiprocessor system includes an execution unit operative on the basis of a virtual storage scheme and a cache memory having entries designated by logical addresses from the execution unit. For controlling the cache memory, a first address array containing entries designated by the same logical addresses as the cache memory and storing control information for the corresponding entries of the cache memory is provided in association with a second address array having entries designated by physical addresses and storing translation information for translation of physical addresses to logical addresses for the entries.

Abstract: A data storage system with data mirroring and reduced access time data retrieval includes at least one pair of rotating data storage media each having a plurality of generally identical data records. Each rotating data storage medium includes position indicators, for providing one or more indications of the rotational position of each of the rotating data storage media with respect to its associated fixed position read/write mechanism. A position monitor receives the rotational position indications from each rotating data storage medium and computes and monitors the rotational position of each rotating storage medium with respect to its associated read/write mechanism.

Abstract: A nonvolatile memory (28) in a data processor (10) is capable of being progressively programmed and/or accessed in a user determined number of sections. A user can program and/or access what appears to the user to be reprogrammable nonvolatile memory (28) at a same address when in actuality the user is programming and accessing sequential sections of nonvolatile memory (28). Nonvolatile information stored in nonvolatile control bits (20) is used to control which section of the nonvolatile memory is connected to a communication bus and is thus accessible to the user. When the user desires to write and/or access a new section of nonvolatile memory (28), either the user directly asserts one of the nonvolatile control bits (20) using software, or the nonvolatile control (24) asserts one of the nonvolatile control bits (20) using hardware.

Abstract: A computer complex is provided with a mechanism for message delivery and redelivery in a controlled manner through the use of distributed shared memory. This provides a mechanism for overall computer system complex operation from a plurality of consoles which are registered or identified to the system and which particularly enhances capabilities for remote operation. In this way the complex can be made to look like a single system. Direct communication between any pair of systems is provided, say, by channel-to-channel adapters. Message information is maintained in each system which can also communicate with shared storage to establish update level information regarding locally maintained message information.

Abstract: Information needed by application programs from a secondary storage is cached in a cache memory which is organized in multiple levels, each level having multiple entries, the entries of each level receiving information of a predetermined category, each entry being accessible independently. Links are defined between entries of one level of the cache memory and entries at another level of the cache memory, the links corresponding to information relationships specified by a user of information stored in the secondary storage. In response to a request to a file system from an application for needed information, the needed information is fetched into the cache, and in connection with fetching the needed information, other information is prefetched from the system of files which is not immediately needed. Quotas are established on information which may be fetched from a secondary storage into the cache, the quotas being applicable to file contents within a file and to the number of files within a directory.

Abstract: Before a memory access request is applied to a memory, a request receive signal is generated and applied to a controller. The controller retrieves information from a request information buffer having a limited memory space. The information is to be returned to a unit which has issued the request and is stored in a reply buffer. The transfer of the information into the reply buffers induces the acceptance of a new request before the completion of the actual access to the memory.

Abstract: A method and apparatus for supporting multiple DMA channels by splitting data transfers for each channel into sequences of data slices and interleaving on a slice-by-slice basis. While the control of transfer resources may be shifted among the DMA channels, the ordering of the data slices for each channel is preserved. The present invention also discloses a circuit architecture capable of supporting the multiple interleaving DMA channels. The circuit architecture comprises a dual-port memory, channel sequencer, and channel interleave control. The dual-port memory stores slices of data to be transferred through the channels. A channel sequencer maintains the channel ordering of data slices in the dual-port memory. A channel interleave control unit allows channels to interleave their data transfers by monitoring the channel interleave size, current data transfer count and total transfer count per channel.

Abstract: A memory mapping system for use by a port adapter in a computer facilitates access to named data buffers in host memory. The system generally comprises a mechanism that enables the adapter to efficiently translate the data buffer name to physical address locations in host memory without knowledge of the memory management policies of the computer. Specifically, the system includes various data structures and pointers that allow the port adapter to view host memory in "port pages" when accessing memory locations of a named data buffer. The data locations are virtually, but not physically, contiguous and the invention provides efficient identification of the physical addresses of the locations.

Abstract: A data memory management unit for providing cache access in a signal processing system. A programmable translation unit and an address processor are used to alter the manner in which addresses are translated and the cache is filled, respectively. The translation unit and address processor operate in accordance with a selected cache replacement mechanism, which is selected so that the cache is filled in a manner most likely to have a high hit rate for the processing algorithm currently in operation.

Abstract: A dual-access protected electronic mass memory unit, the various elements of which comprise a plurality of logic boards connected to at least one peripheral controller (CNT.sub.1, CNT.sub.2) of the information processing system (H) to which the unit belongs. The electronic memory unit includes at least one electronic disk unit (DEI.sub.1, DEI.sub.2) including a motherboard (11, 21) containing the corresponding controller (CNT.sub.1, CNT.sub.2), and a plurality of daughter boards (12-13, 22-23) comprising an equal number of memory planes connected among one another two-by-two, the first of them being connected to the motherboard. The central processor and the electronic disk unit are connected by the motherboard to a first and second parallel bus (B.sub.1, B.sub.2).

Abstract: An apparatus and method for maintaining variable data in a non-volatile electronic memory device comprises a shifter array (106) which provides a shifter value to shifter register (104). Shifter register (104) uses 8-bit column decoder (110) to specify which of a plurality of overlapping storage units in array (94) will store variable data provided from register (92). Address register (112) specifies to row decoder (116) which of two rows in shifter array (106), pointer array (118) and array (94) will be accessed by read and write operations. Pointer array (118) stores an index specifying which of the two rows contains the most recently updated variable data. Shifter register (104) uses 8-bit column decoder (108) to specify which of a plurality of adjacent storage units in pointer array (118) will store the index. OR gate (98) specifies when to replace an overlapping storage unit in array (94) and an adjacent storage unit in pointer array (118).

Abstract: A data storage system having a local processor and a plurality of memory storage elements is used for storing data from one or more external CPUs. The storage system includes a plurality of memory buffers, each coupled to a separate memory storage element. A data path control circuit is programmed by the local processor to control the transfer of data between the external CPUs and the memory buffers. Two interface circuits are coupled between the external CPUs and the memory buffers to provide two data paths for transferring data between the external CPUs and the memory buffers. The data path control circuit contains two independent sequencing circuits for selecting memory buffers. This allows one data path to be used for reading or writing to a number of the memory buffers while the other data path is simultaneously used for a different operation for the rest of the memory buffers.

Abstract: An IC memory card connectable to a host has a storage implemented as an EEPROM, and a control circuit for controlling the storage to write data transferred from the host to the memory card in the storage. The control circuit has latches for temporarily holding input data and an address representative of a particular storage location of the storage for storing the data which are transferred from the host, a clock input terminal for receiving from the host a first clock for causing the latches to hold the data, and a clock generator for generating a second clock for writing the data in the storage.

Abstract: An address translator has an improved data comparison circuit for comparing two pieces of data having n bits, e.g., 12 bits. In the data comparison circuit, cell circuits compare two pieces of data for every corresponding 4 bits. When a match is detected in the comparison of a set of 4 bits, a signal representative of the comparison result of the lower-order bits is bypassed. Hence, delay of signal propagation which may occur in the cell circuit in which the match is detected is reduced.