Abstract: A portable electronic device comprises a control section comprising CPU and RAM which turn off a power if a keyboard has not been operated for a predetermined period of time, set whether the power is to be turned off, and set the predetermined period of time in which the power is turned off. The RAM saves data which is being processed when the power is turned off, even after the power is turned off. The CPU enables the process which is interrupted when the power is turned off to be resumed, on the basis of the data stored in the RAM and determines whether to resume the process which is interrupted when the power is turned off.

Abstract: An address translation device for translating a virtual address belonging to each one of a plurality of virtual spaces into a real address, comprises: a first circuit for holding a plurality of virtual space identifiers indicating the corresponding virtual spaces; a second circuit for holding first selecting information specifying a virtual space identifier for a virtual space to which a virtual address for an instruction belongs from among the plurality of virtual space identifiers held in the first means, and second selecting information specifying a virtual space identifier for a virtual space to which a virtual address for an operand belongs; a third circuit for selecting any one of the virtual space identifiers specified by the first selecting information and the second selecting information held in the second means, depending on whether the virtual address to be translated is for the instruction or the operand; and a fourth circuit for translating the virtual address into a corresponding real address de

Abstract: A circuit for allowing greater user control over a cache memory is implemented in a data processor (20). Cache control instructions have been implemented to perform touch load, flush, and allocate operations in data cache (54) of data cache unit (24). The control instructions are decoded by both instruction cache unit (26) and sequencer (34) to provide necessary control and address information to load/store unit (28). Load/store unit (28) sequences execution of each of the instructions, and provides necessary control and address information to data cache unit (24) at an appropriate point in time. Cache control logic (60) subsequently processes both the address and control information to provide external signals which are necessary to execute each of the cache control instructions. Additionally, cache control logic (60) provides an external transfer code signal which allows a user to know when a cache transaction is performed.

Abstract: A multiprocessor system of the present invention has an address bus, a data bus, first and second processors, four access queues, and a shared memory divided into four banks. The four access queues are constituted by first-in first-out memories for buffering a plurality of access-request addresses transmitted through the address bus. Even if continuous access requests are addressed to one bank of the shared memory, a succeeding access request need not wait for a previous access request to be finished. Accordingly, the throughput of the system can be improved greatly.

Abstract: A plurality of processors and a particular processor use a common memory. A requesting processor requesting communication with the particular processor writes data at a predetermined address of the common memory which corresponds to the requesting processor. Upon writing the data into the common memory, an interruption signal is produced to interrupt the particular processor. The particular processor processes the interruption signal and determines which of the plurality of processors requested the communication with the particular processor and reads data from the address area in the common memory which corresponds to the requesting processor, thereby enabling communication between the requesting and particular processors to be conducted.

Abstract: This invention relates principally to methods and apparatus for recording data on and reading data from a magnetizable medium using a scanning tunneling technique. Conventional rigid probes used in scanning tunneling microscopy (STM) and the like are replaced by a compliant magnetic probe wherein the STM image is a convolution of magnetic forces and the surface topography of the magnetizable medium. Data can be written to the medium by increasing the tunneling current, reducing the scan rate, and/or increasing the magnetization of the compliant magnetic tunneling tip in order to alter the local magnetic characteristics of the medium. A preferred material for the compliant probe is a free-standing thin film of iron vacuum-deposited on a glass substrate and later removed therefrom.The compliant probe of the invention may also be employed for imaging the local surface magnetization of a magnetic member.

Abstract: A storage control system includes an apparatus and method for user control of a storage interface to operate a storage medium to store data obtained by a real-time data acquisition system. Digital data received in serial format from the data acquisition system is first converted to a parallel format and then provided to the storage interface. The operation of the storage interface is controlled in accordance with instructions based on user control input from a user. Also, a user status output is displayed in accordance with storage data obtained from the storage interface. By allowing the user to control and monitor the operation of the storage interface, a stand-alone, user-controllable data storage system is provided for storing the digital data obtained by a real-time data acquisition system.

Abstract: Bipolar transistors are used to select memory cells of single-bit line output type. Bit lines are connected to the emitters of the selecting bipolar transistors, respectively. The collectors of the selecting bipolar transistors are connected to one another, thus forming a node. A potential which is higher than the ground potential and lower than a power-supply potential is applied to the gate of any one of the bipolar transistors which has been selected. This potential determines the maximum voltage of the bit lines. A current-sensing amplifier amplifies the difference between a reference potential and the potential of the collector node of the bipolar transistors, thus generating two output signals. A sense amplifier converts these output signals into a signal at a CMOS logic level, whereby the data stored in a selected memory cell is read out.

Abstract: Enables a host (hypervisor) to access any location in any guest zone in a large memory, when host and guest operands have small addresses that cannot access locations outside of their own zones. System hardware/microcode provides a particular number of windows for host use. Each CPU in the system has one or more window access registers (WARs), and one or more window registers (WRs). The host uses a load WAR instruction to designate each page frame (PF) in the host zone to be used as a host window, and each PF is associated with a respective window number. When the host receives an interception signal requiring the host to access a guest location represented by a guest zone identifier and a guest small address, the host designates one of its window numbers for an access to this guest location.

Abstract: A plurality of physical addresses are derived from address information stored in an address memory of a bridge or other multi-port communication device, wherein the stored address information does not directly specify all the addresses. In a first embodiment, the stored addressing information specifies a single address value from a first block of preferably consecutive address values. A processor uses the first address value to derive a second address value from a second, different block of preferably consecutive address values, and then assigns both as, e.g., port addresses. In a second embodiment of the invention, the address memory stores address information which specifies a range of preferably consecutive address values, for instance, the first and last address values of the range. A processor fetches these address values from the address memory, identifies all address values within the range, and assigns them as, e.g., port addresses.

Abstract: A circuit for providing the function of a dual port FIFO circuit including a first bank of single port random access memory, a second bank of single port random access memory, apparatus for sequentially writing every other piece of sequential data to an alternate one of the first and second [memory] banks of single port memory, and apparatus for simultaneously reading the earliest written piece of sequential data from the one [each] of the first and second [memory] banks of single port memory not being written during the period data is being written to the other of the [memory] banks of single port memory. By using two banks of single port memory, the cost of dual port memory typically used for a FIFO circuit is substantially reduced.

Abstract: A data processing network includes multiple processing devices, multiple memory cards of main storage, and a shared interface. Each of the memory cards includes memory arrays, an internal register for temporarily storing a pointer data word read from the arrays, and logic circuitry. When one of the processing devices sends a tag bit extraction or tag bit insertion command to one of the memory cards, the pointer to be modified is retrieved from a selected address in the memory arrays and latched into the internal register. The logic circuitry provides the tag bits to an AND logic gate and provides the AND gate output to the processor in the case of tag bit extraction. For tag bit insertion, the circuitry applies the pointer from the arrays and a tag bit input from the processor, as inputs to a multiplexer and provides the multiplexer output back to the selected address in the arrays.

Abstract: A computer system wherein a paging technique is used to expand the usable non-volatile memory capacity beyond a fixed address space limitation. The computer system of the preferred embodiment includes a flash memory component for storing non-volatile code and data including a system BIOS in the upper 128K of memory. The useful BIOS memory space is effectively increased while maintaining the address boundary of the upper 128K region. The address space of the non-volatile memory device is logically separated into distinct pages of memory (Pages 1-4). Page 1, Page 3 and Page 4 may be individually swapped into the address space originally occupied by Page 1 (the swappable page area). In the preferred embodiment, Page 2 is held static and thus is not used as a swap area. Each of the swappable pages contain processing logic called swapping logic used during the swapping or paging operation. The swapping logic operates in conjunction with paging hardware to effect the swapping of pages into the swappable page area.

Abstract: A read buffering system employs a bank of FIFOs to hold sequential read data for a number of data streams being fetched by a computer. The FIFOs are located in the memory controller, so the system bus is not used in the memory accesses needed to fill the stream buffer. The buffer system stores addresses used for read requests made by a CPU, and if a next sequential address is then detected in a subsequent read request, this is designated to be a stream (i.e., sequential reads). When a stream is thus detected, data is fetched from DRAM memory for addresses following the sequential address, and this prefetched data is stored in one of the FIFOs. A FIFO is selected using a least-recently-used algorithm. When the CPU subsequently makes a read request for data in a FIFO, this data can be returned without making a memory access, and so the access time seen by the CPU is shorter.

Abstract: A method and apparatus for shifting data in an array of storage elements (22-37) in a data processing system (10). In one form, the present invention uses multiplexer (MUX) logic (38) and Shift Control signals to selectively couple storage elements (22-37) to latches (39-42). In this manner, data values can be serially scanned into and out of the array for test purposes without requiring a duplicate set of latches. The MUX logic 38 couples one storage element (22-37) to each latch (39-42). Then MUX logic 38 decouples those storage elements (22-37). Next, MUX logic 38 couples an adjacent storage element (22-37) to each latch (39-42). In this manner, the storage elements (22-37) in one row and the latches (39-42) mimic the functionality of a shift register.

Abstract: A method for achieving multilevel inclusion in a computer system with first and second level caches. The caches align on a "way" basis by their respective cache controllers communicating with each other which blocks of data they are replacing and which of their cache ways are being filled with data. On first and second level cache read misses the first level cache controller provides way information to the second level cache controller to allow received data to be placed in the same way. On first level cache read misses and second level cache read hits, the second level cache controller provides way information to the first level cache controller, which places data in the indicated way. On processor writes the first level cache controller caches the writes and provides the way information to the second level cache controller which uses the way information to select the proper way for data storage. An inclusion bit is set on data in the second level cache that is duplicated in the first level cache.

Abstract: A method and an apparatus for configuring multiple absolute address spaces are disclosed which simultaneously operate a plurality of virtual machines (VMs) respectively having operating systems on a single real computer by allocating a plurality of logical address spaces to an absolute address space. A different absolute address space is allocated to each of the VMs, whereby the respective VMs can access a main storage with a designated address without adding a constant to the designated address.

Abstract: A reconfigurable set associative cache memory can be reconfigured from 2.sup.x way to 2.sup.y way set associative cache memory by effectively merging a predetermined number of least significant bits of the tag field of the main memory address with the line field of the main memory address. The effective merging is provided by logically merging least significant bits of the tag field with a reconfiguration designation. As a result, Y-X+1 different configurations of cache memory can be obtained using the Y-X least significant bits of the tag field merged with the cache memory address.

Abstract: A disc drive translation and defect management method and apparatus. The method and apparatus includes an index table to translate a host computer's logical cylinder request into an arbitrarily designated physical cylinder location in the disc drive system. Once the physical cylinder is located, the physical head and sector location is determined with a quick, relatively simple mathematical translation. If a defect is present on the indexed physical cylinder in question, the index table provides a defect flag and a pointer which points into a predetermined entry of a defect table. The selected entry in the defect table provides a defect offset value for the physical location in question. The offset value is added to the physical cylinder, head and sector location to push it into a defect-free physical location.

Abstract: A data register file system is provided in a microprocessor having a pipelined execution unit that employs the data register file to store operands and results of its instruction executions. The data register file system includes a plurality of data registers, each of which stores one of the operands and results. A pointer table has a plurality of pointer registers, each storing an address of one of the data registers. A first address generation logic is coupled to the pointer table and the pipelined execution unit for generating a first set of pointer table addresses to access a first group of the pointer registers for the addresses of a first group of the data registers which are required by the execution of a first floating point instruction.