Abstract: A method of increasing the amount of directly addressable memory address locations that can be allocated to RAM. An initialization routine is executed to identify ROM's in reserved memory address space that are to be reallocated. Suitable address space in extended memory is located and the ROM's are mapped into extended memory address space. A ROM access interceptor routine is implemented to trap ROM accesses and direct them to the reallocated address space. A ROM access handler routine is implemented to contain the ROM execution and to restore the computer system to a condition where it can continue execution of application or system software after the ROM access is completed. Memory addresses in reserved address space formerly allocated to ROM's can be reallocated to RAM or other memory devices.

Abstract: A cache controller tag ram is configured into a two ways, each way including tag and valid-bit storage for associatively searching the directory for cache data-array addresses. The two ways, a right way and a left way, each store tag addresses. First means are provided for asserting a flush signal upon the condition that a warm start reset is recognized or a power up condition is recognized. Logic causes all pending write requests to be withdrawn in response to the flush signal. The directory is cleared by setting all valid, write protect and least recently used (LRU) bits to zero in both of the ways. Subsequent write requests use a line fill algorithm to ensure that correct data is written into the directory by choosing which way to select for a line fill after the bits have been cleared.

Abstract: A microprocessor incorporating a cache memory with a selective purge operation includes a control register for storing control information including page information for controlling a purge operation for purging a predetermined page divided in the cache memory, a setting portion for transferring the control information to the control register; a comparator for comparing a target page address indicated by the control information stored in the control register with an address stored in the cache memory; and an issue portion for providing a purge command to indicate the start of execution of the purge operation to the comparator based on the control information stored in the control register only when the target page address agrees with an address in the cache memory.

Abstract: A combiner/memory system interconnects a plurality of computer systems using for example the new HIPPI standard link. The combiner system includes it's own internal storage for rapid shared access to all connected computer systems. The combiner/memory system includes a smart switch for reading header information, arbitrating messsages and connecting computers to each other or to the internal shared storage. The system also includes a mechanism for synchronization of cooperating processes.

Abstract: A method of controlling data which is stored into a common storage in a multiprocessor system having a common storage which can be accessed from a plurality of computers is disclosed. Particularly, a method of controlling shared data using an extended storage as a common storage is disclosed. The copy of the data of a part of or all of a shared data set in an input/output device and the copy data control information to control the copied data are stored into the common extended storage. In the case of accessing the data in the common extended storage, the mutual exclusion among a plurality of computers and the consistency control of the data are realized by referring to the control information stored in the common extended storage.

Abstract: A decision circuit receives input addresses of instructions to be executed and data addresses to which the instructions are to be applied. The decision circuit either allows the execution of the instruction or prohibits the execution of the instruction if the instruction leads to a false operation or to a fraudulent attempt to divulge the system contents. A buffer register stores the instruction addresses and subsequently presents them to the decision circuit simultaneously with the data addresses. This device applies particularly to the protection of electronic integrated circuit memory cards.

Abstract: A semiconductor memory device comprises eight memory arrays arranged in one column. A peripheral circuit is arranged in the central portion of the eight memory arrays, two column decoders being arranged with the peripheral circuit interposed therebetween. Each of the eight memory arrays is provided with a row decoder. A plurality of first column selecting lines are provided so as to cross the three memory arrays arranged on one side of the peripheral circuit from the column decoder. In addition, a plurality of second column selecting lines are provided so as to intersect with the three memory arrays arranged on the other side of the peripheral circuit from the column decoder.

Abstract: A computer system includes first and second processors each having a virtual cache memory, a main memory, a bus coupled to the main memory and the processors, and apparatus for addressing the cache associated with each processor for providing that the data in each virtual cache stores data from the same physical location in main memory at a same index position in each virtual cache, a memory management unit (MMU) coupled to each processor such that addressing information is transferred to each memory management unit to indicate the virtual address of data to be written to the virtual cache, the memory management unit generating from the virtual address a physical address, and determining whether any other virtual cache includes data from the same physical memory positions.

Abstract: An acceleration device for enhancing the speed of synchronous writes in a computer system includes a novel control means, in one embodiment a device driver, and stable storage having an access time on the same order of magnitude as the access time of the main memory in the computer system. In one embodiment, the novel device driver is interposed in the operating system of the computer between the proprietary kernel and one or more peripheral storage unit device drivers. The novel device driver intercepts I/O commands, for example, synchronous write commands, from the operating system that are intended for one of the peripheral storage unit device drivers and subsequently copies the data specified in the write command from main memory of the computer to the stable storage of the acceleration device. The stable storage is operated as a cache and upon one of a set of predetermined conditions being satisfied, selected data stored in the stable storage are transferred, i.e.

Abstract: A cache memory hierarchy having a first level write through cache memory and a second level write back cache memory is provided to a computer system having a CPU, a main memory, and a number of DMA devices. The first level write through cache memory responds to read and write accesses by the CPU, and snoop accesses by the DMA devices, whereas the second level write back cache memory responds to read and write accesses by the CPU as well as the DMA devices. Additionally, the first level write through cache memory is a relatively large cache memory designed to provide a high cache hit rate, whereas the second level write back cache memory is a relatively small cache memory designed to reduce accesses to the main memory. Furthermore, the first level write through cache memory reallocates its cache lines in response to CPU read misses only, whereas the second level write through cache memory reallocates its cache lines in response to CPU write misses only.

Abstract: An expandable memory system including a central memory controller and one or more plug-in memory modules, each memory module having an on-board memory module controller coupled in a serial network architecture which forms a memory command link Each memory module controller is serially linked to the central memory controller. The memory system is automatically configured by the central controller, each memory module in the system is assigned a base address, in turn, to define a contiguous memory space without user intervention or the requirement to physically reset switches. The memory system includes the capability to disable and bypass bad memory modules and reassign memory addresses without leaving useable memory unallocated.

Abstract: A bit addressing system is disclosed in which on N-bit long addressing for the main storage is executed by means of a computation including a plurality of fields in an addressing operand. When there exist predetermined fields in the addressing operand, the value determined by the fields is regarded as the value for the bit unit in the two's complement representation, and a base address and a bit offset are generated by adding the value obtained by shifting the bit unit value by M bits in the direction of the lower order bits, to the address of the byte unit. Namely, it becomes possible to designate two effective addresses of a base address which is a byte address and a bit offset which is the bit displacement from the base address by means of a single operand. The range of designation of the bit offset is from -2.sup.N-1 bit to (+2.sup.N-1 -1) bit, and it is possible to designate the range of 2.sup.N+M bits as bit addresses.

Abstract: Dynamic partitioning of cache storage into a plurality of local caches for respective classes of competing processes is performed by a step of dynamically determining adjustments to the cache partitioning using a steepest descent method. A modified steepest descent method allows unpredictable local cache activities prior to cache repartitioning to be taken into account to avoid readjustments which would result in unacceptably small or, even worse, negative cache sizes in cases where a local cache is extremely underutilized. The method presupposes a unimodal distribution of cache misses.

Abstract: A data processing system capable of accessing multiple virtual address spaces wherein a an access register translation is performed when obtaining an origin address (STO) of a translation table to be used for address translation of a logical address into a real address. If an access register designated by an instruction has a value equal to a predetermined value, another STO stored in a control register is used instead of the STO obtained by the access register translation. Registers are provided for storing results of detection as to whether or not each of the access registers has a value equal to the predetermined value and a sector is provided selecting either the STO in the control register or the STO obtained by the access register translation based on the stored results of detection, thus eliminating a process to discriminate the values of the access registers at each access to the virtual address spaces.

Abstract: A processor data memory address generator is adapted to receive a control word from a program controller receiving instructions from a program memory addressed by an instruction counter and producing a program signal addressed to an arithmetic and logic unit. The instruction counter is incremented by a clock signal and reset by the program controller. The control word comprises location information and selection information and the address generator is adapted to produce a data address having a first part comprising bits of said location information and a second part formed by a selected set of bits of the address of the current instruction identified by said selection information.

Abstract: A data storing device has at least first to third registers. When the first register is accessed, the second register is set into an accessible state in a preset cycle succeeding to a cycle in which the first register is accessed. The same address as that of the second register is assigned to the third register and access to the third register is inhibited in a preset cycle in which the second register is accessed. An access control circuit controls permission/inhibition of access to the second and third registers.

Abstract: A programmable and testable memory address decoder for a computer system where a static random access memory device is used to store memory configuration information. The computer system includes a processor which is coupled to the memory address decoder via data and address lines. The memory address decoder includes an SRAM for storing a memory map which associates memory attributes with memory ranges or blocks of memory. The memory attributes include: memory residence, caching, write protection of memory ranges, and the decoding of other memory modules. The present invention also includes control logic, a read-back register, and a mode register for controlling the loading and read back verification of the SRAM. The control logic operates the memory address decoder in one of four modes. These modes include: 1) power-up mode, 2) programming mode, 3) read back mode, and 4) normal operation mode. One of these modes is selected by loading the mode register with a value corresponding to the desired mode.

Abstract: A computer system incorporating a memory controller which is capable of working with a write-back cache which operates using burst operations and with ISA and EISA bus masters. A state machine is provided for use with the cache controller and a state machine is provided for use with the EISA and ISA bus masters. When a bus master has requested data which is present only in the cache controller and a write-back operation must be performed, the memory controller halts the operation of the EISA and ISA bus masters until the data can be fully written back by the cache controller. In the case of an EISA bus master, this halting operation is performed by stretching the clocking signal which forms the synchronizing signal for the EISA bus. In the case of ISA bus masters, this halting is done by providing a wait state indication to the ISA bus masters. The state machine responsible for the memory controller cooperating with the bus masters is paused and the state machine for the cache controller is activated.

Abstract: In an information processing apparatus composed of two or more processor units each including a cache memory and a processor which accesses stored data via the cache memory, and a main storage, a cache memory control method in which, using information concerning control object data, such as identification of a storage area and whether or not the data are program data, a judgment is made as to whether or not the data has a high possibility of being used by another processor. If the data has a high possibility of being used by another processor, the cache memory is controlled by the store-through system. If the data has a low possibility of being used by another processor, the cache memory is controlled by the store-in system.

Abstract: A tag comparator and bank selector for a set-associative cache in a computer system operates in a minimum time so that a cache hit or miss signal is generated early in a memory cycle. The data memory of the cache has two (or more) banks, with a tag store for each bank, and the two banks are accessed separately and in parallel using the index (low order address bits) while the tag translation is in progress. Two bit-by-bit tag compares are performed, one for each tag store, producing two multibit match indications, one bit for each tag bit in each tag store. These two match indications are applied to two separate dynamic NOR gates, and the two outputs applied to a logic circuit to detect a hit and generate a bank-select output. There are four possible outcomes from the compare operation: both banks miss, left bank hits, right bank hits, and both banks hit. The later condition indicates a possible ambiguity, and neither data item should be used, so a miss is signalled.