Abstract: A method of transferring data words that include data bytes within a computer having a main memory, a processor and a cache memory, with the processor being able to cause data words to be transferred in a burst mode from the cache memory to the main memory in one of a plurality of predetermined sequences, includes the following steps: (1) determining which data words of a group of data words located in the cache memory include data bytes which have been modified, (2) selecting one sequence of data words of the plurality of predetermined sequences of data words which includes (a) all of the data words of the group of data words that include data bytes which have been modified, and (b) a minimum number of data words of the group of data words that include no data bytes which have been modified, and (3) causing the one sequence of data words selected in the selecting step to be transferred in the burst mode from the cache memory to the main memory.

Abstract: A block substitution method of a cache memory incudes the steps of storing data integrity information with a main memory for each block of the cache memory and calculating a non-reference period of each block. The non-reference periods of the blocks are compared to determine an order of the blocks based on the non-reference periods and a difference between the non-reference period of the block having a longest non-reference period and the non-reference period of other blocks is calculated. Data integrity in the block having the longest non-reference period is examined and when there is no data integrity in that block the data integrity in other blocks is examined in the order of the non-reference period. A block having a longest non-reference period among the blocks having the data integrity is determined and the determined block is selected as a block to be substituted by a new data block when the difference is smaller than a predetermined value. New data is loaded to the selected block.

Abstract: A method of copying system data at the time of updating of a main control apparatus in a system using a computer, and a copying adaptor used for this method. The method comprises replacing the control program memory of a main control apparatus, when it is updated, by an adaptor having the function of transferring and retaining system data, transferring and storing the system data stored in the system data memory of the main control apparatus to and in the adaptor, and connecting the adaptor to a new main control apparatus to transfer the system data so as to store the system data in the system data memory of the new main control apparatus.

Abstract: A simple mixed first level cache memory system (50) includes a level 1 cache (52) connected to a processor (54)by read data and write data lines (56) and (58). The level 1 cache (52) is connected to level 2 cache (60) by swap tag lines (62) and (64), swap data lines (66) and (68), multiplexer (70) and swap/read Line (72). The level 2 cache (60) is connected to the next lower level in the memorv hierarchy by write tag and write data lines (74) and (76). The next lower level in the memory hierarchy below the level 2 cache (60) is also connected by a read data line (78) through the multiplexer (70) and the swap/read line (72) to the level 1 cache (52). When processor (54) requires an instruction or data, it puts out an address on lines (80). If the instruction or data is present in the level 1 cache (52), it is supplied to the processor (54) on read data line (56).

Abstract: A system for dynamically allocating memory to a file buffer cache manager and a virtual memory space manager is provided. The file buffer cache memory is time stamped at times of acquisition and access, and the acquired virtual memory space memory is time stamped at times of acquisition and access. If the file buffer cache manager or the virtual memory address manager requests memory, the time stamps of the memories acquired by the file buffer cache manager and the virtual memory space manager are compared. The piece of memory which has the earlier time stamp is preempted and allocated to the manager which has requested memory.

Abstract: A method is described of programming a memory array on a single integrated circuit so that a portion of each data word is characterized as CAM, with the remaining portion of each data word functioning as RAM. The programmable memory array is partitioned into CAM and RAM subfields by disabling the comparators in each memory cell in selected columns of CAM cells to create RAM-functioning cells. Said partitioning may be re-programmed to enable the comparators in said RAM-functioning cells to be re-enabled, so that said cells may participate in subsequent comparisons to a search word. The described memory array permits direct retrieval and storage of associated information in RAM-functioning cells corresponding to data words which are determined to match a given search word. This direct retrieval and storage process can efficiently be utilized without computing or decoding an address for the associated information.

Abstract: A cache management system and method monitors and controls the contents of cache memory coupled to at least one host and at least one data storage device. A cache indexer maintains a current index of data elements which are stored in cache memory. A sequential data access indicator, responsive to the cache index and to a user selectable sequential data access threshold, determines that a sequential data access is in progress for a given process and provides an indication of the same. The system and method allocate a micro-cache memory to any process performing a sequential data access. In response to the indication of a sequential data access in progress and to a user selectable maximum number of data elements to be prefetched, a data retrieval requestor requests retrieval of up to the selected maximum number of data elements from a data storage device. A user selectable number of sequential data elements determines when previously used micro-cache memory locations will be overwritten.

Abstract: A method and apparatus for translating a large logical address as a large virtual address (LVA) when a dynamic address translation (DAT) mode is on. Each LVA is separated into three concatenated parts: 1. a highest-order part (ADEN) for indexing into an access directory (AD) to locate an entry (ADE) for locating one access list (AL); 2. an intermediate part (ALEN) for indexing into a selected AL to access an entry (ALE) that enables location of an associated conventional address translation table which represents a conventional size virtual address space; and 3. a low-order DAT virtual address (VA) part having the same size as a conventional type of virtual address. The low-order DAT VA part is translated by the associated conventional address translation table. If a carry signal is generated during the creation of the low-order DAT VA part, then a change in the selection of an ALE results.

Abstract: Interrupt circuitry for a processor comprises a plurality of interrupt inputs, an interrupt output, combinatorial logic with a plurality of combinatorial logic inputs connected to the plurality of interrupt inputs and with a combinatorial logic output connected to the interrupt output wherein an interrupt output signal at the interrupt output is a function of interrupt signals at the plurality of interrupt inputs; and an interrupt mode select connected to the combinatorial logic wherein an interrupt mode select signal from the interrupt mode select controls the function. The interrupt mode select signal from the interrupt mode select selects the function to be either AND or OR.

Abstract: A comparing unit compares an address of data written into a main memory by an external device with an address of data stored in a cache memory, and a masking unit masks specific bits obtained by a result in said address comparing unit. An invalidating unit invalidates data stored in the cache memory corresponding to the specific bits masked by the masking unit. Therefore, inconsistency between the main memory and the cache memory can be prevented, even when the data are transferred by using a block transfer process.

Abstract: A data generating apparatus for sequentially generating data includes a binary counter, a setting circuit, a match detecting circuit, and a selector group. The binary counter responds to a clock signal for sequentially generating data. The setting circuit sets a data preceding the data to be skipped. The match detecting circuit detects a match of the data set by the setting circuit with the data generated by the binary counter. The selector group supplies "1" to the binary counter when a match is not detected by the match detecting circuit, and "2" to the binary counter when a match is detected by the match detecting circuit. The binary counter adds "2" to the preceding data when a match is detected by the match detecting circuit to skip the desired data.

Abstract: A cache memory system for use during vector processing in a processor. The processor contains a central processing unit (CPU) and a main memory. The system includes a vector cache memory, a first address register, a main memory address calculation unit, and a cache address calculation unit. The first register stores a first address associated with an instruction executed by the CPU. The main memory address calculation unit is coupled to the first address register for calculating a second address utilizing the first address and vector stride data associated with said executed instruction. The second address is utilized to access the main memory. The cache address calculation unit is coupled to both the first address register and the main memory address calculation unit for calculating the third address utilizing portions of the first address and portions of the second address. The third address is utilized to access the vector cache memory.

Abstract: A method and system are disclosed for permitting high concurrency of access during backup copying of designated data stored within a storage subsystem which includes multiple storage devices coupled to the data processing system via a storage subsystem control unit having subsystem memory therein. Data within each storage device is accessed utilizing a Unique Control Block (UCB), which identifies a selected storage device, and an associated data retrieval command sequence which identifies the data to be accessed. Portions of the data copied to subsystem memory within the subsystem storage control unit as sidefiles from a first storage device may be accessed utilizing a Unique Control Block (UCB) associated with an alternate storage device by associating a selected data retrieval command sequence therewith which identifies the data as stored within the subsystem memory.

Abstract: A controller for a first in first out (FIFO) memory comprises detector logic for detecting any difference between the number of addresses in the memory into which data is written and the number of addresses in the memory from which data is read. Comparator logic connected to the detector logic generates a request data transfer signal in response to said difference becoming greater than or equal to a threshold. Threshold select logic connected to the comparator logic is responsive to data having first and second portions being written to the memory. The threshold select logic sets the threshold to a first value when the first portion is being written and sets the threshold to a second value, greater than the first value, when the second portion is being written.

Abstract: A processor module generates a data write request and sends data specified thereby to each of two data buffers respectively provided in two data storage units, each having a data storage device, such as a magnetic disc device. When the data has been completely written into each of the data buffers, a write completion response is sent back to the processor module from each of the data storage units. When the processor module has received the write completion responses from the data storage units, it recognizes that the data write request has been completed.

Abstract: A new type of superconducting memory is described. The composition of superconducting ceramic material used in the memory has been altered in order to expedite the formation of non-superconducting regions formed of grain boundaries. Non-superconducting regions may also be formed of lattice defects. Magnetic flux is trapped within the non-superconducting regions (grain boundaries or lattice defects). Information can be stored in terms of whether or not magnetic flux is trapped.

Abstract: A novel memory hashing system is disclosed. The system converts an address into a hashed address of the form (B,C) where B is a module number in a multi-module memory system and C is an offset in the module. The system can be shown to have no pathological cases for any stride value less than some predetermined value. An apparatus according to the present invention is conveniently implemented in a pipelined architecture which allows one address value to be calculated each memory cycle. The present invention utilizes a special matrix calculated from a primitive polynomial for calculating the hashed addresses. The conversion of any given address requires one row of the matrix. The entries of the matrix may be stored in ROM. Alternatively, the required row of the matrix may be calculated in response to receiving the address which is to be convened to the hashed address.

Abstract: Apparatus and methods for a cache controller preserving cache consistency and providing multiple outstanding operations in a cache memory structure supporting a high performance central processor unit (CPU). An external cache array is coupled to both the CPU and a cache controller (CC), and is subblocked to reduce miss rate. The CC is coupled via a high speed bus to a main memory. A cache directory in the CC tracks usage of the external cache, and is organized to support a choice of bus protocols for buses intercoupling the CC to the main memory. The cache directory consists of tag entries, each tag entry having an address field and multiple status bit fields, one status bit field for each subblock. The status bit fields, in addition to shared-, owner-, and valid-bits, have a pending-bit which, when set, indicates a pending uncompleted outstanding operation on a subblock, and will prevent the CPU from overwriting the corresponding subblock.

Abstract: A variable value monitoring system and method acquires and displays data information words having addresses within a certain range. In one mode of operation, data information words having addresses within a predetermined range are selected and stored in a shadow RAM and only changes in that data are presented to a viewer. The viewer can select the display format for a panel of data contained within the predetermined range of addresses. A FIFO memory temporarily stores the variable values of selected data information words. A flag memory stores flag bits at internal addresses corresponding to each address in a predetermined block of external addresses. Status bit are provided for each data word addressed by the predetermined block of addresses and means are provided for logically comparing the flag bits with corresponding status bits and for storing a data information word in the FIFO if the logical comparison is true.

Abstract: In buffer storage equipment, storage control is carried out by a pipeline having two stages including a stage for executing out-of-order processing for processing a succeeding request with priority and a stage for not executing out-of-order processing. By this storage control, a request processing order is guaranteed at the stage for not executing out-of-order processing and a request is caused to wait at the stage for executing out-of-order processing.