Abstract: Disclosed are a display device for preventing loss of line patterns and a method of manufacturing the display device. The display device includes a substrate having an active area, a non-active area, and a pad portion formed at one side of the non-active area, printed circuit films disposed in the pad portion so as to be spaced a first distance apart from an edge of the substrate in a first direction and to be spaced apart from each other in a second direction that intersects the first direction, a first-layer line and a second-layer line disposed within the first distance between the printed circuit films and the edge of the substrate so as to be spaced apart from each other in the first direction, and island-shaped dummy patterns disposed in the same layer as the second-layer line in a region between two adjacent ones of the printed circuit films.

Abstract: Semiconductor devices and methods of manufacturing semiconductor devices with differing threshold voltages are provided. In embodiments the threshold voltages of individual semiconductor devices are tuned through the removal and placement of differing materials within each of the individual gate stacks within a replacement gate process, whereby the removal and placement helps keep the overall process window for a fill material large enough to allow for a complete fill.

Abstract: A semiconductor device structure is provided. The structure includes a semiconductor substrate having a well pick-up region and an active region adjacent to the well pick-up region. The semiconductor device structure also includes a first fin structure with a first width and a third fin structure with a third width formed adjacent to each other in the well pick-up region and a second fin structure with a second width and a fourth fin structure with a fourth width formed adjacent to each other in the active region. The first width is different than the second width, the third width is different than the fourth width, and the first width is substantially equal to or greater than the third width.

Abstract: A semiconductor device includes a plurality of blocks on a substrate. Trenches are disposed between the plurality of blocks. Conductive patterns are formed inside the trenches. A lower end of an outermost trench among the trenches is formed at a level higher than a level of a lower end of the trench adjacent to the outermost trench. Each of the blocks includes insulating layers and gate electrodes, which are alternately and repeatedly stacked. Pillars pass through the insulating layers and the gate electrodes along a direction orthogonal to an upper surface of the substrate.

Abstract: A semiconductor device and a manufacturing method thereof are disclosed. In which a first opening and a second opening are vertically separated, and are no longer restricted by the condition that a deep upper opening needs to be filled with a thick photoresist when a TSV nested hole in vertical communication forms a middle opening and lower opening, thereby satisfying devices with different thicknesses requirements. The design is no longer restricted by the lateral process of the TSV nested hole, thereby enhancing the flexibility of the design. In the photolithography process, the deep hole does not need to be filled with the photoresist, the photoresist does not need to be thick, thereby reducing the complexity of the photolithography process and improving the exposure effect. The first metal layer and the second metal layer are directly led out via a first trench, thereby simplifying the process and reducing the production cost.

Abstract: Techniques regarding non-SAC semiconductor devices are provided. For example, one or more embodiments described herein can comprise an apparatus, which can further comprise a gate positioned adjacent a channel region of a semiconductor body for a field effect transistor. The gate can comprise a metal liner, and wherein the metal liner is an interface between a first metal layer of the gate and a second metal layer of the gate.

Abstract: A semiconductor device includes etch stop films formed on the first gate electrode, the first source region, the first drain region, and the shallow trench isolation regions, respectively. First interlayer insulating films are formed on the etch stop film, respectively. Deep trenches are formed in the substrate between adjacent ones of the first interlayer insulating films to overlap the shallow trench isolation regions. Sidewall insulating films are formed in the deep trenches, respectively. A gap-fill insulating film is formed on the sidewall insulating film. A second interlayer insulating film is formed on the gap-fill insulating film. A top surface of the second interlayer insulating film is substantially planar and a bottom surface of the second interlayer insulating film is undulating.

Abstract: A three-dimensional memory device includes an alternating stack of source layers and drain layers located over a substrate, gate electrodes vertically extending through each of the source layers and the drain layers of the alternating stack, memory films laterally surrounding a respective one of the gate electrodes, and semiconductor channels laterally surrounding a respective one of the memory films and connected to a respective vertically neighboring pair of a source layer and a drain layer. An array of memory openings can vertically extend through the alternating stack, and each of the gate electrodes can be located within a respective one of the memory openings.

Abstract: A vertical memory device includes gate electrodes spaced apart from each other in a first direction. Each of the gate electrodes extends in a second direction. Insulation patterns extend in the second direction between adjacent gate electrodes. A channel structure extends in the first direction. The channel structure extends through at least a portion of the gate electrode structure and at least a portion of the insulation pattern structure. The gate electrode structure includes at least one first gate electrode and a plurality of second gate electrodes sequentially stacked in the first direction on the substrate. Lower and upper surfaces of a first insulation pattern are bent away from the upper surface of the substrate along the first direction. A sidewall connecting the lower and upper surfaces of the first insulation pattern is slanted with respect to the upper surface of the substrate.

Abstract: A semiconductor structure is provided that includes a first FinFET device for low power applications and a second FinFET device for non-low power applications. The first FinFET device has an active fin height, i.e., channel height, which is less that an active fin height of the second FinFET device. The active fin height adjustment is achieved utilizing an isolation structure that has a constant height in the region including the first FinFET device and the region including the second FinFET device.

Abstract: A semiconductor device and method for fabricating the same are provided. The semiconductor device includes a substrate including a cell region, a core region, and a boundary region between the cell region and the core region, a boundary element isolation layer in the boundary region of the substrate to separate the cell region from the core region, a high-k dielectric layer on at least a part of the boundary element isolation layer and the core region of the substrate, a first work function metal pattern comprising a first extension overlapping the boundary element isolation layer on the high-k dielectric layer, and a second work function metal pattern comprising a second extension overlapping the boundary element isolation layer on the first work function metal pattern, wherein a first length of the first extension is different from a second length of the second extension.

Abstract: Flip chip LEDs incorporate multi-layer reflectors and light transmissive substrates patterned along an internal surface adjacent to semiconductor layers. A multi-layer reflector may include a metal layer and a dielectric layer containing conductive vias. Portions of a multi-layer reflector may wrap around a LED mesa including an active region, while being covered with passivation material. A substrate patterned along an internal surface together with a multi-layer reflector enables reduction of optical losses. A light transmissive fillet material proximate to edge emitting surfaces of an emitter chip may enable adequate coverage with lumiphoric material. An emitter chip may be elevated with increased thickness of solder material and/or contacts, and may reduce luminous flux loss when reflective materials are present on a submount.

Abstract: A method for forming an antifuse on a substrate is provided, which comprises: forming a first conductive material on the substrate; placing the first conductive material in an electrolytic solution; performing anodic oxidation on the first conductive material to form a nanowire made of the first conductive material and surrounded by a first dielectric material formed during the anodic oxidation and to form the antifuse on the nanowire; and forming a second conductive material on the antifuse to sandwich the antifuse between the first conductive material and the second conductive material.

Abstract: An avalanche diode is provided and includes a first semiconductor region and a second semiconductor region. At a deeper position, the avalanche diode includes a third semiconductor region having an impurity concentration lower than that of the first semiconductor region, and a fourth semiconductor region having an impurity concentration lower than that of the second semiconductor region. At a further deeper position, the avalanche diode includes a fifth semiconductor region having an impurity concentration lower than that of the third semiconductor region. In a plan view, the first semiconductor region overlaps at least a part of the third semiconductor region, the second semiconductor region overlaps at least a part of the fourth semiconductor region, and the third and fourth semiconductor regions overlap the fifth semiconductor region.

Abstract: A semiconductor device is disclosed. The semiconductor device may include a substrate including a first active pattern, the first active pattern vertically protruding from a top surface of the substrate, a first source/drain pattern filling a first recess, which is formed in an upper portion of the first active pattern, a first metal silicide layer on the first source/drain pattern, the first metal silicide layer including a first portion and a second portion, which are located on a first surface of the first source/drain pattern, and a first contact in contact with the second portion of the first metal silicide layer. A thickness of the first portion may be different from a thickness of the second portion.

Abstract: A micro-LED display panel is disclosed. The micro-LED display panel includes: a plurality of unit substrates, each of which is formed with a plurality of electrode pads; a plurality of pixels, each of which includes a first micro-LED chip, a second micro-LED chip, and a third micro-LED chip mounted corresponding to the electrode pads; and a mesh arranged over the plurality of unit substrates. The mesh has pixel spacing portions covering at least some exposed areas of the plurality of unit substrates between the pixels and a plurality of openings accommodating the corresponding pixels. The micro-LED display panel is constructed such that the reflection of external light by the exposed areas of the substrate between the pixels and the exposed areas of the electrode pads disposed on the unit substrates is reduced. This construction improves the contrast characteristics and black characteristics of a display and achieves seamlessness in the micro-LED display panel.

Abstract: A semiconductor device and method of manufacturing a semiconductor device are provided. The semiconductor device includes a semiconductor substrate and a semiconductor layer located on the substrate; at least one shallow trench and at least one deep trench. Each of the at least one shallow trench and the at least one deep trench extending from a first major surface of the semiconductor layer. Sidewall regions and base regions of the trenches comprise a doped trench region and the trenches are at least partially filled with a conductive material contacting the doped region. The shallow trenches terminate in the semiconductor layer and the deep trench terminates in the semiconductor substrate.

Abstract: A qubit device includes an elongated thin film uninterrupted by Josephson junctions, a quantum device in electrical contact with a proximal end of the elongated thin film, and a ground plane that is co-planar with the elongated thin film and is in electrical contact with a distal end of the elongated thin film, in which the thin film, the quantum device, and the ground plane comprise a material that is superconducting at a designed operating temperature.

Abstract: A printed circuit board (PCB) includes an insulating layer with an upper surface and a lower surface opposite to the upper surface; a first conductive pattern on the upper surface of the insulating layer; a second conductive pattern on the lower surface of the insulating layer; an aluminum pattern that covers at least a portion of an upper surface of the first conductive pattern; and a first passivation layer that covers at least a portion of sides of the first conductive pattern and that prevents diffusion into the first conductive pattern.

Abstract: An inverter that includes an n-type field effect transistor (nFET) and a p-type field effect transistor (pFET) vertically stacked one atop the other and containing a buried metal semiconductor alloy strap that connects a drain region of the nFET to a drain region of the pFET is provided. Also, provided is a cross-coupled inverter pair with nFETs and pFETs stacked vertically.