Abstract: A semiconductor device manufacturing method is presented. The method entails providing a semiconductor structure comprising a substrate, one or more semiconductor fins on the substrate, and a trench isolation structure around each semiconductor fin, wherein the trench isolation structure comprises a first component intersecting an extension direction of the semiconductor fin and a second component parallel with the extension direction; etching the trench isolation structure to expose a portion of the semiconductor fin; forming a patterned buffer layer on the semiconductor structure covering the second component and having an opening exposing the first component; forming an insulation layer in the opening, with upper surfaces of the insulation layer and the semiconductor fin substantially on the same horizontal level; and removing the buffer layer. This inventive concept reduces, if not eliminates, oxide loss in Single Diffusion Break (SDB) region.

Abstract: A printed circuit board (PCB) includes an insulating layer with an upper surface and a lower surface opposite to the upper surface; a first conductive pattern on the upper surface of the insulating layer; a second conductive pattern on the lower surface of the insulating layer; an aluminum pattern that covers at least a portion of an upper surface of the first conductive pattern; and a first passivation layer that covers at least a portion of sides of the first conductive pattern and that prevents diffusion into the first conductive pattern.

Abstract: A method for forming a microelectromechanical device is shown. The method comprises forming a cavity in a semiconductor substrate material, wherein the semiconductor substrate material comprises an opening for providing access to the cavity through a main surface area of the semiconductor substrate material. In a further step, the method comprises forming a support structure having a support structure material different from the semiconductor substrate material to close the opening at least partially by mechanically connecting the main surface area of the semiconductor substrate material with the bottom of the cavity. Furthermore, the method comprises a step of forming a lamella structure in the main surface area above the cavity such that the lamella structure is held spaced apart from the bottom of the cavity by the support structure.

Abstract: A flexible dielectric substrate (102) defines a LESD mounting region (120) including two conductive filled vias (105, 106) extending through the flexible dielectric substrate (102) and the LESD mounting region is substantially surrounded by two conductive frame portions (112, 116). The frame portions are in electrical connection with the conductive filled vias (105, 106), respectively. The conductive filled vias (105, 106) form conductive features in the mounting region (120) that are co-planar with each other.

Abstract: A leadframe has a peripheral frame. A die attach pad (DAP) is positioned inwardly and downwardly of the peripheral frame. Two spaced apart parallel arms engage one side of the DAP. In one embodiment the arms are portions of a U-shaped strap.

Abstract: The present invention provides a method for crystallizing a metal oxide semiconductor layer, a semiconductor structure, a method for manufacturing a semiconductor structure, an active array substrate, and an indium gallium zinc oxide crystal. The crystallization method includes the following steps: forming an amorphous metal oxide semiconductor layer on a substrate; forming an oxide layer on the amorphous metal oxide semiconductor layer; forming an amorphous silicon layer on the oxide layer; and irradiating the amorphous silicon layer by using a laser, so as to heat the amorphous silicon layer, where the heated amorphous silicon layer heats the amorphous metal oxide semiconductor layer, so that the amorphous metal oxide semiconductor layer is converted into a crystallized metal oxide semiconductor layer.

Abstract: Disclosed are an array substrate and a method for manufacturing the same, which belong to the technical field of display, and are able to solve the technical problem that the existing process for manufacturing array substrates is too complex. The array substrate includes a plurality of sub-pixel units formed on a base substrate. Each of the sub-pixel units comprises a thin film transistor and a second pixel electrode. An active layer of the thin film transistor is made of an oxide semiconductor. The second pixel electrode is made of a plasma treated transparent oxide semiconductor. The array substrate provided by the present disclosure can be used in an IPS or FFS liquid crystal display device.

Abstract: A semiconductor device includes a substrate having a cell region and a peripheral region, a thyristor on the cell region, a MOS transistor on the peripheral region, and a first silicide layer on the substrate adjacent to the thyristor on the cell region. Preferably, the thyristor includes: a first semiconductor layer, a second semiconductor layer, a third semiconductor layer, and a fourth semiconductor layer on the cell region, vertical dielectric patterns in the first semiconductor layer, the second semiconductor layer, the third semiconductor layer, and the fourth semiconductor layer, and first contact plugs on the fourth semiconductor layer.

Abstract: A semiconductor may include a substrate including a cell array region and a TSV region, an insulation layer disposed on the substrate and having a recess region on the TSV region, a capacitor on the insulation layer of the cell array region, a dummy support pattern disposed on the insulation layer of the TSV region and overlapping the recess region, when viewed in plan, and a TSV electrode penetrating the dummy support pattern and the substrate.

Abstract: An active device array substrate including a first scan line, a first data line, a second data line, a first active device, a first pixel electrode, a second active device, a second pixel electrode, and a first shielding pattern layer is provided. The first active device includes a first gate electrically connected to the first scan line, a first semiconductor pattern layer, a first source electrically connected to the first data line, and a first drain. The second active device includes a second gate electrically connected to the first scan line, a second semiconductor pattern layer, a second source electrically connected to the second data line, and a second drain. The first shielding pattern layer is overlapped with the first semiconductor pattern layer and the second semiconductor pattern layer. The first shielding pattern layer is overlapped with the second data line and not overlapped with the first data line.

Abstract: Embodiments of the invention include vertically oriented long channel transistors and methods of forming such transistors. In one embodiment, a method of forming such a transistor may include forming a fin on a semiconductor substrate. Embodiments may also include forming a spacer over an upper portion of the fin and a lower portion of the fin not covered by the spacer may be exposed. Embodiments may also include forming a gate dielectric layer over the exposed portion of the fin. A gate electrode may then be deposited, according to an embodiment. Embodiments may include exposing a top portion of the fin and forming a first source/drain (S/D) region in the top portion of the fin. The second S/D region may be formed by removing the semiconductor substrate to expose a bottom portion of the fin and forming the second S/D region in the bottom portion of the fin.

Abstract: A package structure including an integrated fan-out package and plurality of conductive terminals is provided. The integrated fan-out package includes an integrated circuit component, a plurality of conductive through vias, an insulating encapsulation having a first surface and a second surface opposite to the first surface, and a redistribution circuit structure. The insulating encapsulation laterally encapsulates the conductive through vias and the integrated circuit component. Each of conductive through vias includes a protruding portion accessibly revealed by the insulating encapsulation. The redistribution circuit structure is electrically connected to the integrated circuit component and covers the first surface of the insulating encapsulation and the integrated circuit component.

Abstract: An integrated circuit (IC) device may include a substrate having an active device layer. The integrated circuit may also include a first defect layer. The first defect layer may have a first surface facing a backside of the active device layer. The integrated circuit may further include a second defect layer. The second defect layer may face a second surface opposite the first surface of the first defect layer.

Abstract: A semiconductor device capable of holding data for a long time is provided. The semiconductor device includes a first transistor, a second transistor, and a circuit. The first transistor includes a first gate and a second gate. The first transistor includes a first semiconductor in a channel formation region. The first gate and the second gate overlap with each other in a region with the first semiconductor provided therebetween. The second transistor includes a second semiconductor in a channel formation region. A first terminal of the second transistor is electrically connected to a gate of the second transistor and the second gate. A second terminal of the second transistor is electrically connected to the circuit. The circuit has a function of generating a negative potential. The second semiconductor has a wider bandgap than the first semiconductor.

Abstract: The present invention provides a laminated member that prevents contact of a semiconductor chip and an external leading terminal etc. without increasing the number of components. The laminated member is a laminated member having a three-layer structure, comprising: an upper highly thermally conductive layer; a lower highly thermally conductive layer; and an intermediate layer having a low thermal expansion coefficient, wherein the above-described laminated member is larger than the above-described semiconductor chip in a plan view, and wherein a height position of the above-described first peripheral edge area is located at a certain distance below a height position of the above-described first bonding area, and a height position of the second peripheral edge area of the above-described second bonding area is located at a certain distance above a height position of the above-described second bonding area.

Abstract: Provided are electronic devices having a two-dimensional (2D) material layer. The electronic device includes an electrode layer that directly contacts an edge of the 2D material layer. The electrode layer may include a conductive material having a high work function or may have a structure in which an electrode layer includes a conductive material having a high work function and an electrode layer includes a conductive material having a low work function.

Abstract: Structures, devices and methods are provided for forming nanowires on a substrate. A first protruding structure is formed on a substrate. The first protruding structure is placed in an electrolytic solution. Anodic oxidation is performed using the substrate as part of an anode electrode. One or more nanowires are formed in the protruding structure. The nanowires are surrounded by a first dielectric material formed during the anodic oxidation.

Abstract: A method for forming an antifuse on a substrate is provided, which comprises: forming a first conductive material on the substrate; placing the first conductive material in an electrolytic solution; performing anodic oxidation on the first conductive material to form a nanowire made of the first conductive material and surrounded by a first dielectric material formed during the anodic oxidation and to form the antifuse on the nanowire; and forming a second conductive material on the antifuse to sandwich the antifuse between the first conductive material and the second conductive material.

Abstract: A semiconductor device may include an active fin, an element isolation film on a lower portion of the active fin and a gate structure crossing over the active fin. The gate structure may include first and second sides. The device may also include a source region and a drift region adjacent the first and second sides of the gate structure, respectively. The drift region may have a first impurity concentration. The device may further include a drain region that is in the drift region and may have a second impurity concentration higher than the first impurity concentration, a first trench that is in the drift region and may have a depth less than a height of the active fin, and an upper embedded insulating layer in the first trench. The gate structure may overlap a portion of the drift region and a portion of the first trench.

Abstract: A package (e.g., a wafer level package (WLP)) including one or more redistribution layers to fan out the contact pads of the one or more dies within an integrated circuit structure. An example package includes a die having a contact pad exposed at a frontside thereof. The package also includes a redistribution layer disposed over the frontside of the die. The redistribution layer includes metallization extending through a nano-composite material, which may be formed from a dielectric material with a nano-filler material disposed therein. The metallization is electrically coupled to the contact pad of the die. By incorporating the nano-composite material in the redistribution layer, the coefficient of thermal expansion (CTE) of the redistribution layer more closely matches the CTE of the die, which prevents or eliminates undesirable warpage of the redistribution layers.