Abstract: A method of manufacturing an electronic device formed in a cavity may include, on a first substrate having a bottom surface and a top surface, forming a first side wall of a certain height along a periphery on the bottom surface to surround an electronic circuit disposed on the bottom surface; forming a via communicating between the bottom surface and the top surface, forming of the via including stacking a first stop layer and a second stop layer sequentially on a portion of the bottom surface of the first substrate corresponding to the via and etching the first substrate to form a through-hole corresponding to the via, a rate of etching the first substrate being greater than that of the first stop layer and a rate of etching the first stop layer being greater than that of the second stop layer; forming a second side wall of a certain height along a periphery on a top surface of the second substrate; and aligning and bonding the first side wall and the second side wall.

Abstract: A method includes bonding a first semiconductor chip on a second semiconductor chip, applying an etching process to the first semiconductor chip and the second semiconductor chip until a metal surface of the second semiconductor chip is exposed, wherein as a result of applying the etching process, an opening is formed in the first semiconductor chip and the second semiconductor chip and plating a conductive material in the opening to from a conductive plug.

Abstract: The present disclosure relates to a conductive layer, a thin film transistor and manufacturing methods therefor, an array substrate and a display device, in the field of displays. The conductive layer comprises: a metal layer and an organophosphorus-metal complex covering the metal layer. In the embodiments of the present disclosure, the organophosphorus-metal complex is manufactured on the surface of the metal layer to form the conductive layer. The conductive layer is adopted as an electrode material. In one aspect, the organophosphorus-metal complex has conductivity and can prevent the surface of metal from making contact with oxygen, thereby avoiding metal oxidation under the premise of not affecting the performances of the electrode when serving as a material of the electrode in a TFT. In the other aspect, the organophosphorus-metal complex can increase a binding force between the metal and photoresist and avoids stripping of the photoresist.

Abstract: A semiconductor device includes trench structures that extend from a first surface into a semiconductor body. The trench structures include a gate structure and a contact structure that extends through the gate structure, respectively. Transistor mesas are between the trench structures. Each transistor mesa includes a body zone forming a first pn junction with a drift structure and a second pn junction with a source zone. Diode regions directly adjoin one of the contact structures form a third pn junction with the drift structure, respectively.

Abstract: A semiconductor device structure is provided. The structure includes a semiconductor substrate having a well pick-up region and an active region. Each of the well pick-up region and the active region includes a first well region and a second well region that have different conductivity types. There is a well boundary between the first well region and the second well region. A first fin structure is in the first well region of the well pick-up region and second fin structures are in the first well region of the active region. The minimum distance between the well boundary and the first fin structure is greater than the minimum distance between the well boundary and one of the second fin structures that is closest to the well boundary.

Abstract: A semiconductor device and a method for fabricating the semiconductor device are provided. The method includes forming a first composite structure, including a plurality of first composite layers, on a substrate, and forming a second composite structure, including a plurality of second composite layers on a surface portion of the first composite structure. The method also includes forming a first mask layer covering a sidewall of the second composite structure and a surface portion of the first composite structure and exposing at least another surface portion of the first composite structure. In addition, the method includes forming a second mask layer, on a surface portion of the second composite structure and spaced apart from the first mask layer by a first annular opening. Further, the method includes etching a top first layer of the first composite layers and a top first layer of the second composite layers.

Abstract: The present disclosure provides a packaging adhesive, a packaging method, a display panel, and a display device. The packaging adhesive includes a frit, an organic solvent, and a material with a thermal expansion coefficient larger than that of the frit. Using the packaging adhesive provided by the present disclosure, the thermal expansion coefficient of the packaging adhesive from which the organic solvent is removed may be enhanced by doping the material with a thermal expansion coefficient larger than that of the frit into existing glass cement, so that in a packaging process using laser radiation, an expansion volume of the packaging adhesive when heated is increased. In this way, a gap between the packaging adhesive and an array substrate is effectively reduced, and a packaging effect is improved.

Abstract: A semiconductor device includes a plurality of blocks on a substrate. Trenches are disposed between the plurality of blocks. Conductive patterns are formed inside the trenches. A lower end of an outermost trench among the trenches is formed at a level higher than a level of a lower end of the trench adjacent to the outermost trench. Each of the blocks includes insulating layers and gate electrodes, which are alternately and repeatedly stacked. Pillars pass through the insulating layers and the gate electrodes along a direction orthogonal to an upper surface of the substrate.

Abstract: A semiconductor device may include a first sensor configured to sense light having a wavelength within a first wavelength range from incident light and generates a first electrical signal based on the sensed light and a second sensor configured to sense light having a wavelength within a second, different wavelength range from the incident light and generates a second electrical signal based on the sensed light. The first and second sensors may be electrically connected to each other via an intermediate connector, and the first sensor and the second sensor may share a pixel circuit that is electrically connected thereto via the intermediate connector. The first and second wavelength ranges may include infra-red and visible wavelength ranges, respectively. The first and second wavelength ranges may include different visible wavelength ranges.

Abstract: Memory devices and methods of forming memory devices are described. The memory devices comprise a substrate with at least one film stack. The film stack comprises a polysilicon layer on the substrate; a bit line metal layer on the polysilicon layer; a cap layer on the bit line metal layer; and a hardmask on the cap layer. The memory device of some embodiments includes an optional barrier metal layer on the polysilicon layer and the bit line metal layer is on the barrier metal layer. Methods of forming electronic devices are described where one or more patterns are transferred through the films of the film stack to provide the bit line of a memory device.

Abstract: An MTJ structure having vertical magnetic anisotropy is provided. The MTJ structure having vertical magnetic anisotropy can comprise: a substrate; an artificial antiferromagnetic layer located on the substrate; a buffer layer located on the artificial antiferromagnetic layer, and including W or an alloy containing W; a first ferromagnetic layer located on the buffer layer, and having vertical magnetic anisotropy; a tunneling barrier layer located on the first ferromagnetic layer; and a second ferromagnetic layer located on the tunneling barrier layer, and having vertical magnetic anisotropy. Accordingly, in the application of bonding the artificial antiferromagnetic layer with a CoFeB/MgO/CoFeB structure, the MTJ structure having improved thermal stability at high temperature can be provided by using the buffer layer therebetween.

Abstract: A semiconductor device and method for fabricating the same are provided. The semiconductor device includes a substrate including a cell region, a core region, and a boundary region between the cell region and the core region, a boundary element isolation layer in the boundary region of the substrate to separate the cell region from the core region, a high-k dielectric layer on at least a part of the boundary element isolation layer and the core region of the substrate, a first work function metal pattern comprising a first extension overlapping the boundary element isolation layer on the high-k dielectric layer, and a second work function metal pattern comprising a second extension overlapping the boundary element isolation layer on the first work function metal pattern, wherein a first length of the first extension is different from a second length of the second extension.

Abstract: The present invention relates to the field of semiconductor switches, and relates more particularly to a GaN-based bidirectional switch device. The present invention provides a gate-controlled tunneling bidirectional switch device without Ohmic-contact, which avoids a series of negative effects (such as current collapse, incompatibility with traditional CMOS process) caused by the high temperature ohm annealing process. Each insulated gate structure near schottky-contact controls the band structure of the schottky-contact to change the working state of the device, realizing the bidirectional switch's ability of bidirectional conducting and blocking. Due to the only presence of schottky in this invention, no heavy elements such as gold is needed, and this device is compatible with traditional CMOS technology.

Abstract: An image sensor comprises a first photodiode and a second photodiode having a smaller full-well capacitance than the first photodiode, wherein the second photodiode is adjacent to the first photodiode; a first micro-lens is disposed above the first photodiode and on an illuminated side of the image sensor; a second micro-lens is disposed above the second photodiode and on the illuminated side of the image sensor; and a coating layer disposed on both the first and second micro-lens, wherein the coating layer forms a flat top surface on the second micro-lens and a conformal coating layer on the first micro-lens.

Abstract: A qubit device includes an elongated thin film uninterrupted by Josephson junctions, a quantum device in electrical contact with a proximal end of the elongated thin film, and a ground plane that is co-planar with the elongated thin film and is in electrical contact with a distal end of the elongated thin film, in which the thin film, the quantum device, and the ground plane comprise a material that is superconducting at a designed operating temperature.

Abstract: Provided is a capacitor that has good bonding between the dielectric layer and the conductive layer, has a characteristic of low ESR, and keeps leak current suppressed. The capacitor contains a dielectric layer and a conductive film and is characterized in that the dielectric layer contains an organic compound and a metal compound and that the conductive film contains a conductive material and an organic compound.

Abstract: According to the present disclosure, a method for producing a plurality of semiconductor chips is provided with the following steps: a) providing a composite assembly, including a carrier, a semiconductor layer sequence and a functional layer; b) severing the functional layer by means of coherent radiation along a singulation pattern; c) forming separating trenches in the carrier along the singulation pattern; and d) applying a protective layer, which delimits the functional layer toward the separating trenches, on in each case at least one side surface of the semiconductor chips to be singulated. The singulated semiconductor chips each includes a part of the semiconductor layer sequence, of the carrier and of the functional layer.

Abstract: In one embodiment of the present disclosure, a microfeature workpiece includes at least two features of two different sizes disposed in a dielectric, wherein a width of a first feature is less than or equal to 17 nm and wherein the first feature is filled with cobalt or nickel, and wherein a width of a second feature is greater than 20 nm and wherein the second feature is filled with a stack layer of cobalt or nickel and copper.

Abstract: A light-emitting device includes a substrate, a plurality of light-emitting elements aligned along a longitudinal direction, and a covering member. The substrate includes a pair of first depressed portions and a second depressed portion each opening on a back surface and a bottom surface of a base and positioned on both end sides of the base in the longitudinal direction. The second depressed portion has a width larger than a width of the first depressed portions as measured along a height direction. First metal films extend from inside the first depressed portions to the back surface. A second metal film extends from inside the second depressed portion to the back surface. A solder mask covers at least a part of each of the first metal films and at least a part of the second metal film on the back surface of the base.

Abstract: Methods form an integrated circuit structure that includes complementary transistors on a first layer. An isolation structure is between the complementary transistors. Each of the complementary transistors includes source/drain regions and a gate conductor between the source/drain regions, and insulating spacers are between the gate conductor and the source/drain regions in each of the complementary transistors. With these methods and structures, an etch stop layer is formed only on the source/drain regions.