Abstract: An optoelectronic semiconductor device and an apparatus with an optoelectronic semiconductor device are disclosed. In an embodiment the optoelectronic semiconductor component has an emission region including a semiconductor layer sequence having a first semiconductor layer, a second semiconductor layer, and an active region arranged between the first semiconductor layer and the second semiconductor layer for generating radiation, and a protection diode region. The semiconductor component has a contact for electrically contacting the semiconductor component externally. The contact has a first contact region that is connected to the emission region in an electrically conductive manner. The contact has further a second contact region that is spaced apart from the first contact region and connected to the protection diode region in an electrically conductive manner. The first contact region and the second contact region can be electrically contacted externally by a mutual end of a connecting line.

Abstract: A method for fabricating a stacked electronic device is provided. A first three-dimensional (3D) printing is performed to form a first insulating layer and a plurality of first redistribution layers (RDLs) on a first substrate. A second 3D printing is performed to form a second substrate and a plurality of through-substrate vias (TSVs) on the first insulating layer, in which the plurality of TSVs is electrically connected to the plurality of first RDLs. A third 3D printing is performed to form a second insulating layer and a plurality of second RDLs on the second substrate, in which the plurality of second RDLs is electrically connected to the plurality of TSVs. A plurality of contacts of a third substrate is bonded to the plurality of second RDLs, so that the substrate is mounted onto the second insulating layer. The disclosure also provides a stacked electronic device formed by such a method.

Abstract: A semiconductor structure is provided. A substrate has a first conductivity type. A first well and a second well are formed in the substrate. The first well has a second conductivity type. The second well has the first conductivity type. A doped region is formed in the first well and has the second conductivity type. A gate structure is disposed over the substrate and overlaps a portion of the first well and a portion of the second well. An insulating layer is disposed over the substrate and is spaced apart from the gate structure. A conducting wire is disposed on the insulating layer and includes a first input terminal and a first output terminal. The first input terminal is configured to receive an input voltage. The first output terminal is electrically connected to the doped region.

Abstract: Integrated circuit devices may include a substrate including a flash memory region and a variable resistance memory region, a flash memory cell transistor including a cell gate electrode that overlaps the flash memory region of the substrate, a variable resistance element that overlaps the variable resistance memory region of the substrate, and a select transistor including a select source/drain region that is disposed in the variable resistance memory region of the substrate. The select source/drain region may be electrically connected to the variable resistance element. The substrate may include an upper surface facing the cell gate electrode and the variable resistance element, and the upper surface of the substrate may continuously extend from the flash memory region to the variable resistance memory region.

Abstract: Optoelectronic devices and method of forming the same include an optoelectronic component in a substrate layer. An integrated circuit chip is positioned on the substrate layer. A lens is positioned on the substrate layer directly above the optoelectronic component and above at least part of the integrated circuit chip. The lens has a cut-out portion that accommodates the integrated circuit chip.

Abstract: A semiconductor device includes: an n+ type of silicon carbide substrate, an n? type of layer, first trenches, a p type of region, a p+ type of region, an n+ type of region, a gate electrode, a source electrode, and a drain electrode.

Abstract: The present application provides an array substrate, which comprises a plurality of gate lines, a plurality of data lines, a plurality of thin film transistors, a plurality of pixel electrodes, and a plurality of conductive members. In each of the pixel regions, a control terminal of the TFT is electrically connected with the gate line, an input terminal of the TFT is electrically connected with the data line, and an output terminal of the TFT is electrically connected with the pixel electrode. The output terminal comprises a body, and a first contact and a second contact which are connected with the body. The first contact and one of the conductive members extending into the pixel region are overlapping-disposed and insulated from each other. The second contact and another of the conductive members extending into the pixel region are overlapping-disposed and insulated from each other.

Abstract: Devices and methods of fabricating integrated circuit devices for forming uniform nano sheet spacers self-aligned to the channel are provided. One method includes, for instance: obtaining an intermediate semiconductor device having a substrate, multiple layers disposed on the substrate, and at least one gate structure disposed on the multiple layers; depositing an oxide layer over the device; etching the oxide layer to form replacement sidewall spacers positioned on left and right sides of the at least one gate structure; etching the multiple layers to form at least one stack structure; and forming a plurality of recesses within the at least one stack structure. Also disclosed is an intermediate semiconductor, which includes, for instance: a substrate; and at least one stack structure disposed on the substrate, the at least one stack structure having an upper portion and a base portion, wherein a plurality of recesses are located within the base portion.

Abstract: A semiconductor device includes: a substrate having a cell region and a peripheral region; a thyristor on the cell region; a MOS transistor on the peripheral region; a first shallow trench isolation (STI) between the thyristor and the MOS transistor; and a second STI between the first STI and the MOS transistor. The thyristor further includes: a first semiconductor layer, a second semiconductor layer, a third semiconductor layer, and a fourth semiconductor layer on the cell region; patterned metal layers in the first semiconductor layer; vertical dielectric patterns on the patterned metal layers; and first contact plugs on the fourth semiconductor layer.

Abstract: Embodiments are directed to a method of forming a semiconductor device and resulting structures having an air spacer between a gate and a contact by forming a gate on a substrate and over a channel region of a semiconductor fin. A contact is formed on a doped region of the substrate such that a space between the contact and the gate defines a trench. A first dielectric layer is formed over the gate and the contact such that the first dielectric layer partially fills the trench. A second dielectric layer is formed over the first dielectric layer such that an air spacer forms in the trench between the gate and the contact.

Abstract: An electronic device integration method and integrated electronic device. The integration method may include the steps of preparing a first electronic device by forming an electrically conductive trace overlying a substrate, forming a barrier layer overlying the electrically conductive trace, forming one or more electrically conductive interconnects on the barrier layer, and forming a bonding layer overlying the trace and/or at least partially surrounding the one or more interconnects. The barrier layer is configured to prevent formation of an intermetallic compound between the trace and interconnect structures, while still enabling electrical communication between the trace and interconnect. The integration method may further include the steps of direct bonding the first electronic device to a second electronic device, direct bonding a third electronic device to the second electronic device, and so on.

Abstract: A light-emitting element disclosed in an embodiment comprises: a body having a cavity; first and second lead frames arranged in the cavity; a third lead frame arranged between the first and second lead frames in the cavity; a fourth lead frame arranged between the first and second lead frames and distanced from the third frame in the cavity; a first light-emitting chip arranged on the first lead frame; and a second light-emitting chip arranged on the second lead frame, wherein the body comprises: first and second sides arranged on opposing sides from each other; and third and fourth sides arranged on opposing sides from each other, the first lead frame comprises first and second lead parts protruding toward the first and second sides, the second lead frame comprises third and forth lead parts protruding toward the first and second sides, the third frame comprises a fifth lead part protruding toward the first side, and the fourth lead frame comprises a sixth lead part protruding toward the second side.

Abstract: A semiconductor device and method for fabricating the same are provided. The semiconductor device includes a substrate including a cell region, a core region, and a boundary region between the cell region and the core region, a boundary element isolation layer in the boundary region of the substrate to separate the cell region from the core region, a high-k dielectric layer on at least a part of the boundary element isolation layer and the core region of the substrate, a first work function metal pattern comprising a first extension overlapping the boundary element isolation layer on the high-k dielectric layer, and a second work function metal pattern comprising a second extension overlapping the boundary element isolation layer on the first work function metal pattern, wherein a first length of the first extension is different from a second length of the second extension.

Abstract: A semiconductor device includes a substrate having a first active pattern and a second active pattern, the first active pattern including a first recess region dividing an upper portion thereof into a first portion and a second portion, the second active pattern including a second recess region dividing an upper portion thereof into a first portion and a second portion, a first insulating pattern covering an inner sidewall of the first recess region, and a second insulating pattern covering an inner sidewall of the second recess region. The first insulating pattern and the second insulating pattern include the same insulating material, and a volume fraction of the first insulating pattern with respect to a volume of the first recess region is smaller than a volume fraction of the second insulating pattern with respect to a volume of the second recess region.

Abstract: The present disclosure provides embodiments of package devices and methods for making package devices for a semiconductor die. One embodiment includes a die mounting structure having a finished bond pad that includes a copper bond pad and a cobalt-containing layer over a top surface of the copper bond pad, and a wire bond structure that is bonded to a top surface of the cobalt-containing layer of the finished bond pad, where cobalt-containing material of the cobalt-containing layer is located between a bottom surface of the wire bond structure and the top surface of the copper bond pad such that the cobalt-containing material is present under a center portion of the wire bond structure.

Abstract: A semiconductor device may include a first sensor configured to sense light having a wavelength within a first wavelength range from incident light and generates a first electrical signal based on the sensed light and a second sensor configured to sense light having a wavelength within a second, different wavelength range from the incident light and generates a second electrical signal based on the sensed light. The first and second sensors may be electrically connected to each other via an intermediate connector, and the first sensor and the second sensor may share a pixel circuit that is electrically connected thereto via the intermediate connector. The first and second wavelength ranges may include infra-red and visible wavelength ranges, respectively. The first and second wavelength ranges may include different visible wavelength ranges.

Abstract: Disclosed is a thin film transistor including a gate electrode on a substrate, a gate insulator over the entire surface of the substrate including the gate electrode, a first active layer corresponding to the gate electrode on the gate insulator, a second active layer on or under the first active layer, and a source electrode and a drain electrode spaced apart by a predetermined distance, the source electrode and the drain electrode being connected to the first active layer or the second active layer.

Abstract: An optoelectronic semiconductor component includes an optoelectronic semiconductor chip; and an electrical connection point that contacts the optoelectronic semiconductor chip, wherein the electrical connection point covers the optoelectronic semiconductor chip on the bottom thereof at least in some areas, the electrical connection point includes a contact layer facing toward the optoelectronic semiconductor chip, the electrical connection point includes at least one barrier layer arranged on a side of the contact layer facing away from the optoelectronic semiconductor chip, the electrical connection point includes a protective layer arranged on the side of the at least one barrier layer facing away from the contact layer, the layers of the electrical connection point are arranged one on top of another along a stack direction, and the stack direction runs perpendicular to a main extension plane of the optoelectronic semiconductor chip.

Abstract: This present invention discloses a method for preparing graphene, a thin-film transistor, an array substrate, and a display panel. Above all, an amorphous carbon thin film and a catalyst metal thin film are formed on a base substrate in this order. Then, the catalyst metal thin film and the amorphous carbon thin film are allowed to form a eutectic at a high temperature caused by an excimer laser in a manner of excimer laser irradiation. When the irradiation is finished, the surface temperature of the catalyst metal thin film is drastically decreased, allowing most of carbon atoms of the amorphous carbon thin film to be locked in the catalyst metal thin film and only a small amount of carbon atoms to be precipitated on the lower surface of the catalyst metal thin film, so that a graphene thin film is formed.

Abstract: A method of forming a 3D Hall effect sensor and the resulting device are provided. Embodiments include forming a p-type well in a substrate; forming a first n-type well in a first region surrounded by the p-type well in top view; forming a second n-type well in a second region surrounding the p-type well; implanting n-type dopant in the first and second n-type wells; and implanting p-type dopant in the p-type well and the first n-type well.