Abstract: A semiconductor structure includes a semiconductor substrate, a bottom source/drain layer for a first vertical transistor over the semiconductor substrate, a vertical channel over the source/drain layer, and a metal gate wrapped around the vertical channel, the vertical channel having a fixed height relative to the metal gate at an interface therebetween. The semiconductor structure further includes a top source/drain layer over the vertical channel, and a self-aligned contact to each of the top and bottom source/drain layer and the gate. The semiconductor structure can be realized by providing a semiconductor substrate with a bottom source/drain layer thereover, forming a vertical channel over the bottom source/drain layer, forming a dummy gate wrapped around the vertical channel, and forming a bottom spacer layer and a top spacer layer around a top portion and a bottom portion, respectively, of the vertical channel, a remaining center portion of the vertical channel defining a fixed vertical channel height.

Abstract: Provided are a horizontal light emitting diode (LED) device and a method for fabricating the same. The horizontal LED device includes a sapphire substrate; an n-type GaN layer disposed on the sapphire substrate; an activation layer disposed on the n-type GaN layer; a p-type GaN layer disposed on the activation layer; a current spreading layer disposed on the p-type GaN layer; a p-electrode disposed on the current spreading layer; a plurality of holes exposing the n-type GaN layer through the current spreading layer, the p-type GaN layer, and activation layer; and an n-electrode disposed on the exposed n-type GaN layer and being in ohmic contact with the exposed n-type GaN layer at a plurality of positions on bottom surfaces of the plurality of holes.

Abstract: A semiconductor device has a substrate including a recess and a peripheral portion with through conductive vias. A first semiconductor die is mounted over the substrate and within the recess. A planar heat spreader is mounted over the substrate and over the first semiconductor die. The planar heat spreader has openings around a center portion of the planar heat spreader and aligned over the peripheral portion of the substrate. A second semiconductor die is mounted over the center portion of the planar heat spreader. A third semiconductor die is mounted over the second semiconductor die. First and second pluralities of bond wires extend from the second and third semiconductor die, respectively, through the openings in the planar heat spreader to electrically connect to the through conductive vias. An encapsulant is deposited over the substrate and around the planar heat spreader.

Abstract: A semiconductor substrate has a main surface and formed of single crystal silicon carbide. The main surface includes a central area, which is an area other than the area within 5 mm from the outer circumference. When the central area is divided into square areas of 1 mm×1 mm, in any square area, density of dislocations of which Burgers vector is parallel to <0001> direction is at most 1×105 cm?2. Thus, a silicon carbide semiconductor substrate enabling improved yield of semiconductor devices can be provided.

Abstract: A silicon carbide device is presented that includes a gate electrode disposed over a portion of a silicon carbide substrate as well as a dielectric film disposed over the gate electrode. The device has a contact region disposed near the gate electrode and has a layer disposed over the dielectric film and over the contact region. The layer includes nickel in portions disposed over the dielectric film and includes nickel silicide in portions disposed over the contact region. The nickel silicide layer is configured to provide an ohmic contact to the contact region of the silicon carbide device.

Abstract: Interposer and semiconductor package embodiments provide for the isolation and suppression of electronic noise such as EM emissions in the semiconductor package. The interposer includes shield structures in various embodiments, the shield structures blocking the electrical noise from the noise source, from other electrical signals or devices. The shields include solid structures and some embodiments and decoupling capacitors in other embodiments. The coupling structures includes multiple rows of solder balls included in strips that couple the components and surround and contain the source of electrical noise.

Abstract: A hybridly integrated component includes an ASIC element having a processed front side, a first MEMS element having a micromechanical structure extending over the entire thickness of the first MEMS substrate, and a first cap wafer mounted over the micromechanical structure of the first MEMS element. At least one structural element of the micromechanical structure of the first MEMS element is deflectable, and the first MEMS element is mounted on the processed front side of the ASIC element such that a gap exists between the micromechanical structure and the ASIC element. A second MEMS element is mounted on the rear side of the ASIC element. The micromechanical structure of the second MEMS element extends over the entire thickness of the second MEMS substrate and includes at least one deflectable structural element.

Abstract: Provided is a semiconductor device that includes first and second isolation patterns disposed on a substrate. Alternately stacked interlayer insulating patterns and a conductive patterns are disposed on a surface of the substrate between the first and second isolation patterns. A support pattern penetrates the conductive patterns and the interlayer insulating patterns and has a smaller width than the first and second isolation patterns. First and second vertical structures are disposed between the first isolation and the support pattern and penetrate the conductive patterns and the interlayer insulating patterns. A second vertical structure is disposed between the second isolation pattern and the support pattern and penetrates the conductive patterns and the interlayer insulating patterns. A distance between top and bottom surfaces of the support pattern is greater than a distance between a bottom surface of the support pattern and the surface of the substrate.

Abstract: A semiconductor device includes a semiconductor substrate having a main surface, a MONOS-type memory cell formed over the main surface and having a channel, an n-channel transistor formed over the main surface, and a p-channel transistor formed over the man surface. Nitride films are formed in a manner to contact the top surfaces of the MONOS-type memory cell, the n-channel transistor, and the p-channel transistor. The nitride films apply stress to the channels of the MONOS-type memory cell, the n-channel transistor, and the p-channel transistor.

Abstract: Some embodiments include methods of forming memory cells. An opening is formed over a first conductive structure to expose an upper surface of the first conductive structure. The opening has a bottom level with a bottom width. The opening has a second level over the bottom level, with the second level having a second width which is greater than the bottom width. The bottom level of the opening is filled with a first portion of a multi-portion programmable material, and the second level is lined with the first portion. The lined second level is filled with a second portion of the multi-portion programmable material. A second conductive structure is formed over the second portion. Some embodiments include memory cells.

Abstract: An electro-optical device includes a reflective layer, a light emitting element including a light emitting layer formed between an anode and a cathode, and a driving transistor configured to control a current flowing through the light emitting element. In the same layer as the reflective layer, a relay electrode included in a current path from the driving transistor to the anode is formed with a gap between the relay electrode and the reflective layer. A contact electrode electrically connecting the relay electrode and the anode is formed as a light shielding layer that blocks light entering the gap.

Abstract: A semiconductor substrate has a main surface and formed of single crystal silicon carbide. The main surface includes a central area, which is an area other than the area within 5 mm from the outer circumference. When the central area is divided into square areas of 1 mm×1 mm, in any square area, density of dislocations of which Burgers vector is parallel to <0001> direction is at most 1×105 cm?2. Thus, a silicon carbide semiconductor substrate enabling improved yield of semiconductor devices can be provided.

Abstract: A structure including a first interconnect including a first line overlying a first via and a second interconnect including a second line overlying a second via. The first line and the second line are co-planar. The first interconnect comprises a first conductor, the first conductor comprises a metal silicide including titanium silicide, cobalt silicide, nickel silicide, tungsten silicide, platinum silicide, molybdenum silicide, tantalum silicide, or some combination thereof. The second interconnect comprises a second conductor, the second conductor comprising copper.

Abstract: A semiconductor wafer having a plurality of chip die areas arranged on a wafer in an array, each chip die area including a seal ring area with one or more first sets of polygonal structures. The wafer further comprises scribe line areas between the chip die areas, the scribe line areas including one or more second sets of polygonal structures. The presence of proximate polygonal structures between the scribe line and seal ring areas balance stresses between the chip die areas during wafer dicing operation.

Abstract: Structures and methods of making a flip chip package that employ polyimide pads of varying heights at a radial distance from a center of an integrated circuit (IC) chip for a flip chip package. The polyimide pads may be formed under electrical connectors, which connect the IC chip to a chip carrier of the flip chip package, so that electrical connectors formed on polyimide pads of greater height are disposed at a greater radial distance from the center of the IC chip, while electrical connectors formed on polyimide pads of a lesser height are disposed more proximately to the center of the IC chip. Electrical connectors of a greater relative height to the IC chip's surface may compensate for a gap, produced by heat-induced warpage during the making of the flip chip package, that separates the electrical connectors on the IC chip from flip chip attaches on the chip carrier.

Abstract: An interposer includes a substrate having a contact pad structure and a stud operably coupled to the contact pad structure. A solder ball is seated on the contact pad structure and formed around the stud. The stud is configured to regulate a collapse of the solder ball when a top package is mounted to the substrate.

Abstract: A phase change memory cell and a method for fabricating the phase change memory cell. The phase change memory cell includes a bottom electrode and a first non-conductive layer. The first non-conductive layer defines a first well, a first electrically conductive liner lines the first well, and the first well is filled with a phase change material in the phase change memory cell. A second non-conductive layer is deposited above the first non-conductive layer. A second well is defined by the second non-conductive layer and positioned directly above the first well. A second electrically conductive liner lines at least one wall of the second well such that the second electrically conductive liner is not in physical contact with the first electrically conductive liner. Furthermore, the phase change material is deposited in the second well.

Abstract: A Schottky junction type semiconductor device in which the opening width of a trench can be decreased without deteriorating the withstanding voltage. The cross sectional shape of a trench has a shape of a sub-trench in which the central portion is higher and the periphery is lower at the bottom of the trench, and a p type impurity is introduced vertically to the surface of the drift layer thereby forming a p+ SiC region, which is formed in contact to the inner wall of the trench having the sub-trench disposed therein, such that the junction position is formed more deeply in the periphery of the bottom of the trench than the junction position in the central portion of the bottom of the trench.

Abstract: The embodiments of diffusion barrier layer described above provide mechanisms for forming a copper diffusion barrier layer to prevent device degradation for hybrid bonding of wafers. The diffusion barrier layer(s) encircles the copper-containing conductive pads used for hybrid bonding. The diffusion barrier layer can be on one of the two bonding wafers or on both bonding wafers.

Abstract: Apparatus and associated methods may relate to Magneto-Resistive Sensing Devices (MRSDs). In accordance with an exemplary embodiment, an MRSD comprises an underlying semiconductor device and a magneto-resistive sensor. In some exemplary embodiments, the semiconductor device is processed through most of a standard process flow. After the standard process flow, in various embodiments, a planarization step may be performed to create a more planar top surface. In some embodiments, the magneto-resistive material, which may be made from a Nickel-Iron alloy, called Permalloy, is deposited on the planar surface. A layer of interconnect metallization also may reside in this top region. The magneto-resistive material may contact the topmost layer of metallization of the semiconductor device via contact openings in the planarized surface. In some embodiments, the magneto-resistive material may similarly contact the topmost layer of metallization through these contact openings.