Patents Examined by Jung Ho Kim
  • Patent number: 10530665
    Abstract: In one embodiment, a server instructs one or more networking devices in a local area network (LAN) to form a virtual network overlay in the LAN that redirects traffic associated with a particular node in the LAN to the server. The server identifies a configuration for the particular node based on a node profile for the particular node. The server accesses a configuration interface of the particular node and instructs the particular node to use the identified configuration via the accessed configuration interface.
    Type: Grant
    Filed: April 12, 2017
    Date of Patent: January 7, 2020
    Assignee: Cisco Technology, Inc.
    Inventors: Pascal Thubert, Jean-Philippe Vasseur, Patrick Wetterwald, Eric Levy-Abegnoli
  • Patent number: 10512115
    Abstract: A communication device of handling data transmission comprises configuring a first bearer and a second bearer according to at least one bearer configuration received from a network; encrypting a first packet of a first flow into a first encrypted packet according to an encryption key and a first bearer identity of the first bearer; receiving a first RRC message from the network before transmitting the first encrypted packet to the network successfully, wherein the first RRC message configures the communication device to transmit at least one packet of the first flow via the second bearer to the network; transmitting the first encrypted packet to the network via the first bearer; encrypting a second packet of the first flow into a second encrypted packet according to the encryption key and a second bearer identity of the second bearer; and transmitting the second encrypted packet to the network via the second bearer.
    Type: Grant
    Filed: December 6, 2017
    Date of Patent: December 17, 2019
    Assignee: HTC Corporation
    Inventor: Chih-Hsiang Wu
  • Patent number: 6469565
    Abstract: The present invention relates to a duty cycle adaptive data output buffer of a semiconductor device in which the current driving power of the output buffer is adaptively varied with a duty cycle, to effectively improve noise margin at slow duty cycle. The duty cycle adaptive data output buffer disclosed includes first and second pull-up transistors connected between a power supply voltage and an output terminal; first and second pull-down transistors connected to the output terminal and a ground; duty cycle detector for receiving a duty clock signal, to generate a first control signal at faster duty cycle, and to generate a second control signal at slower duty cycle; a first output driver for driving the first pull-up and pull-down transistors using first and second data signals in response to the first control signal; and a second output driver for driving the second pull-up and pull-down transistors using the first and second data signals in response to the second control signal.
    Type: Grant
    Filed: August 11, 2000
    Date of Patent: October 22, 2002
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Chul-kyu Lee
  • Patent number: 6433618
    Abstract: A variable power device circuit includes a plurality of devices for driving a load. Each of the devices has a body, which is electrically isolated from the substrate. All of the devices are coupled to an output node. The load is also coupled to the output node. A controller selectively turns on individual or multiple ones of the devices based on the electrical requirements of the load.
    Type: Grant
    Filed: September 3, 1998
    Date of Patent: August 13, 2002
    Assignee: International Business Machines Corporation
    Inventors: Claude Louis Bertin, Alvar Antonio Dean, William Robert Patrick Tonti
  • Patent number: 6388508
    Abstract: A current mirror circuit that provides an excellent current that does not deteriorate, even when the power source is lower supply voltage. A mirror current flows in a first MOS transistor when a constant current flows in the MOS transistor from a current source. A subtracter outputs the difference between voltage Vg1 of the gate of the MOS transistor and Voltage Vd1 of the drain, and applies this difference to the gate of a second MOS transistor. When the power-supply voltage of this circuit becomes lower supply voltage and the absolute value of Vd1 decreases, the MOS transistors enter the triode region, and the mirror current decreases when the absolute value of Vd1 decreases, because the difference between Vg1 and Vd1 becomes larger, the drain current of the second MOS transistor increases, and the amount by which the mirror current decreases is counterbalanced.
    Type: Grant
    Filed: November 24, 1999
    Date of Patent: May 14, 2002
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Atsushi Kawasumi
  • Patent number: 6373311
    Abstract: An oscillator circuit produces first and second oscillating logic signals that are of a same frequency and are non-overlapping in a first logic state. This oscillator includes a flip-flop circuit to produce third and fourth oscillating logic signals of opposite polarities, this flip-flop circuit being driven by first and second driving logic signals. First and second logic gates receive the third and fourth logic signals and produce the first and second logic signals, the logic state transitions in the first and second logic signals being produced as a function of the logic state transitions of the third and fourth logic signals. The first and second logic gates are organized so as to introduce a delay into the transitions from a second logic state to the first logic state, in the first and second logic signals, with respect to transitions in the third and fourth logic signals.
    Type: Grant
    Filed: May 25, 2000
    Date of Patent: April 16, 2002
    Assignee: SGS-Thomson Microelectronics S.A.
    Inventors: Olivier Pizzuto, Fran├žois Pierre Tailliet
  • Patent number: 6369641
    Abstract: In one aspect, a bias circuit includes a rectifier, a negative bias level setter, and a negative bias extractor. The rectifier has a rectifier input and a rectifier output. The rectifier is configured to produce at the rectifier output a negative rectified voltage signal from an alternating input signal applied at the rectifier input. The negative bias level setter couples to the rectifier output and provides a path for current establishing the negative rectified voltage signal produced at the rectifier output. The negative bias extractor has an extractor output and an extractor input coupled to the rectifier output. The negative bias extractor is configured to produce at the extractor output a substantially constant negative bias signal from the negative rectified voltage signal produced at the rectifier output.
    Type: Grant
    Filed: September 22, 2000
    Date of Patent: April 9, 2002
    Assignee: Infineon Technologies North America Corp.
    Inventors: Brian J. McNamara, Heinz Banzer, Ludger Verweyen
  • Patent number: 6366156
    Abstract: In some embodiments, In some embodiments, the invention includes an electrical system having a functional unit block (FUB) including field effect transistors (FETs). A distributed forward body bias (FBB) voltage generation system provides at least one body bias signal to at least some of the FETs of the FUB such that the at least some of the FETs have a constant FBB. In some embodiments, the system includes a constant differential voltage generator and a distributed body bias generator to receive a set of differential signals from the constant differential voltage generator and provide at least one body bias signal to at least some of the FETs of the FUB such that the at least some of the FETs have a constant forward body bias. In some embodiments, the system includes multiple body bias generators coupled to corresponding FUBs receive a set of differential signals from a single constant differential voltage generator.
    Type: Grant
    Filed: November 30, 1999
    Date of Patent: April 2, 2002
    Assignee: Intel Corporation
    Inventors: Siva G. Narendra, Vivek K. De, Shekhar Y. Borkar
  • Patent number: 6366159
    Abstract: A dynamic feedback bias circuit. A system utilizing the dynamic bias circuit includes a first bus agent and a second bus agent. The first bus agent generates a first signal having a first voltage swing. The second bus agent has a core which operates at a core operating voltage, the core operating voltage having an amplitude less than the first voltage swing. The second bus agent has an input device which receives the first signal from the first bus agent. The input device of the second bus agent is biased by the dynamic feedback bias circuit to provide a core signal with a voltage swing approximately equal to or less than the core operating voltage.
    Type: Grant
    Filed: February 23, 1998
    Date of Patent: April 2, 2002
    Assignee: Intel Corporation
    Inventor: Babak A. Taheri
  • Patent number: 6366155
    Abstract: Reference voltage regulators and methods for integrated circuit output driver systems generate an initial supplementary current for the integrated circuit output driver system at the reference voltage for a predetermined time period in response to an output enable signal. Preferably, sufficient initial supplementary current is generated to compensate for an initial drop in the reference voltage that is generated by a reference voltage generator upon initial activation of the output driver system. Reference voltage generators according to embodiments of the invention may be included in an integrated circuit output driver system that is responsive to a reference voltage and to an output enable signal, and that varies in current drive capability in response to a current drive control signal. These embodiments of reference voltage regulators include a reference voltage generator that generates the reference voltage for the integrated circuit output driver system.
    Type: Grant
    Filed: July 10, 2000
    Date of Patent: April 2, 2002
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Byung-sick Moon, Mi-seon Kang, Ho-sung Song
  • Patent number: 6359501
    Abstract: The present invention relates to a charge-pumping circuit for low-supply voltage. A small charge-pumping circuit was added at the gates of the original Dickson charge-pumping circuit's each stage for bias voltage and the first transistor group was added between well and gate. The second transistor group was added between the gate and drain of original transistor. Thus, the charge-pumping circuit for low-supply voltage can supply a higher positive or negative voltage.
    Type: Grant
    Filed: February 8, 2001
    Date of Patent: March 19, 2002
    Assignee: Windbond Eelctronics Corp.
    Inventors: Hongchin Lin, Kai-Hsun Chang, Shyh-Chyi Wong
  • Patent number: 6356133
    Abstract: A bus driver circuit includes a plurality of first MOS transistors connected in series between a data input terminal and a data output terminal, and a plurality of second controlling MOS transistors. Sources of said plurality of first MOS transistors are connected to drains of said plurality of second controlling MOS transistors. Also, gates of said plurality of second controlling MOS transistors to control signal source means for selectively turning ON and OFF said plurality of second controlling MOS transistors. The bus driver circuit thus constructed permits selection of optimal rise-up and fall-down transition period for achieving high speed and efficient data transmission.
    Type: Grant
    Filed: February 15, 2000
    Date of Patent: March 12, 2002
    Assignee: NEC Corporation
    Inventor: Hiroshi Kamiya
  • Patent number: 6351163
    Abstract: A reset circuit includes an invertor having one control input terminal to which a positive supply voltage and a potential lower than GND are supplied, and an n-channel transistor having a gate terminal connected to an output terminal of the invertor, a source terminal connected to a potential lower than the GND and a drain terminal connected to the GND.
    Type: Grant
    Filed: April 28, 2000
    Date of Patent: February 26, 2002
    Assignee: Seiko Instruments Inc.
    Inventors: Hirokazu Yoshizawa, Masanao Hamaguchi
  • Patent number: 6351176
    Abstract: A circuit (300) employing metal-oxide-semiconductor (MOS) devices is disclosed. The circuit (300) includes a circuit portion (302) that provides a circuit function, and a body voltage adjust portion (304) which alters the body potential of the transistors within the circuit portion (302). By adjusting the body potentials of the circuit portion (300) transistors, the speed at which the circuit portion (300) can perform its function is increased. A decoder circuit embodiment (800) and sense amplifier embodiments (1200, 1300, 1500, 1600, 1700, 1800, 1900 and 2000) are also disclosed.
    Type: Grant
    Filed: September 13, 1999
    Date of Patent: February 26, 2002
    Assignee: Texas Instruments Incorporated
    Inventor: Theodore W. Houston
  • Patent number: 6342806
    Abstract: An object of the present invention is to economize in power consumption of a semiconductor integrated circuit. The semiconductor integrated circuit has first and second capacitors electrically connected to a control electrode of a transistor. The first capacitor is used to input a signal therein and the second capacitor is used to change a threshold value relative to the input signal.
    Type: Grant
    Filed: July 16, 1999
    Date of Patent: January 29, 2002
    Assignee: Oki Electric Industry CO, Ltd.
    Inventor: Syunsuke Baba
  • Patent number: 6339358
    Abstract: It is possible to reduce the voltage drop on sub-power supply lines for reducing the subthreshold current and thereby prevent the operating speed of a logic circuit from lowering. Main power supply lines are arranged along one side of a rectangular region including a MOS logic circuit whose subthreshold current must be reduced, and a plurality of sub-power supply lines are arranged on the region in the direction perpendicular to the main power supply lines. A plurality of switching MOS transistors for selectively electrically connecting the sub-power supply lines to the main power supply line are dispersedly arranged with respect to the main power supply line. By dispersedly arranging the switching MOS transistors with respect to the main power supply line, it is possible to reduce the equivalent resistance of the sub-power supply lines compared to the case where switching MOS transistors are provided at one place.
    Type: Grant
    Filed: February 28, 2000
    Date of Patent: January 15, 2002
    Assignees: Hitachi, Ltd., Hitachi Device Engineering Co., Ltd.
    Inventors: Masashi Horiguchi, Yasushi Kawase, Takesada Akiba, Yoshinobu Nakagome, Kazuhiko Kajigaya
  • Patent number: 6331798
    Abstract: A control arrangement and method is provided for a power electronic system configured as a high-speed source-transfer switching systems (HSSTSS). The HSSTSS supplies an electrical load with alternating current from either a first source or a second source via respective first and second solid-state switches. The HSSTSS also includes a controller that samples the voltage waveforms of each of the first and second sources to detect when transfer between the sources is desirable, e.g. outages or voltage that is either too low or too high. The controller provides appropriate control signals to control operation of the solid-state switches and transfer supply of the load therebetween. The control arrangement avoids undesirable current flow between sources via a comparison of the voltages of the sources and current in the outgoing source, i.e.
    Type: Grant
    Filed: April 24, 2000
    Date of Patent: December 18, 2001
    Assignee: S&C Electric Company
    Inventors: Raymond P. O'Leary, Michael G. Ennis, Joseph W. Ruta, Anthony F. Segredo
  • Patent number: 6329849
    Abstract: The apparatus for converting a differential input voltage to two fully balanced output currents is achieved by providing a common mode control circuit of a simplified circuit construction to an operational transconductance amplifier. The apparatus includes an operational transconductance amplifier that is comprised of an OTA input section for converting two input voltages of the differential input voltage to a pair of interim output currents and an OTA output section for converting the interim output currents to the output currents, and a common mode controlling circuit for providing a control voltage to the OTA.
    Type: Grant
    Filed: November 12, 1999
    Date of Patent: December 11, 2001
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Zdzislaw Czarnul, Hirotomo Ishii, Kazuhiro Oda
  • Patent number: 6329873
    Abstract: An internal power supply voltage generation circuit includes a main amplifier that supplies a current from an external power supply node to an internal power supply line in accordance with the difference between a reference voltage from a reference voltage generation circuit and an internal power supply voltage on the internal power supply line. The current supply amount by the main amplifier is adjusted by a level adjust circuit, according to the difference between the external power supply voltage and the reference voltage. The internal power supply voltage generation circuit can suppress reduction in the internal power supply voltage in the vicinity of the lower limit area of the differential power supply voltage.
    Type: Grant
    Filed: December 19, 2000
    Date of Patent: December 11, 2001
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventor: Fukashi Morishita
  • Patent number: 6329871
    Abstract: A reference voltage generation circuit includes: a load unit having one end thereof connected to a higher voltage power supply line; an enhancement type n-channel MIS transistor having a drain thereof connected to the other end of the load unit, and a source thereof connected to a lower voltage power supply line; and a source follower circuit using a MIS transistor as a driving element, the source follower circuit having an input end thereof connected to the drain of the n-channel MIS transistor and having an output end thereof connected to a gate of the n-channel MIS transistor. A reference voltage is obtained at the drain of the n-channel MIS transistor. By the constitution, it is possible to obtain a stable reference voltage, and to incorporate the reference voltage generation circuit into an integrated circuit produced by integrating MIS transistors, without introducing an increase in production processes. It is also possible to reduce a consumed current of the reference voltage generation circuit.
    Type: Grant
    Filed: December 22, 2000
    Date of Patent: December 11, 2001
    Assignee: Fujitsu Limited
    Inventor: Masao Taguchi