Abstract: A Norton equivalent implementation of a fail safe bias circuit drives a bus to provide a stable bias voltage which is not affected by an output impedance of a current source. The Norton equivalent implementation has first current source, a bias resistor and a current sink in series. The bias resistor is connected across a pair of differential bus lines so that the current flowing through the bias resistor causes a bias voltage to be generated between the bus lines. The current to the bias resistor is selectively switched on and off to control the bias voltage so that the bias voltage can be turned off during high speed data transfers on the bus.

Abstract: The circuits and methods of the present invention provide rail-to-rail output stages that cancel the non-linear components of the transconductances of transistors used in the output stages, that allow the idling current in the output stages to be controlled by external current sources and device size ratios, and that enable the idling current in the output stages to be maintained independently of manufacturing processes, temperature, and power supply voltages. The output stages generally comprise a complementary subcircuit, a current mirror and an output driver. The output stages receive an input signal and a bias voltage from an external source and responsively produce a push current that feeds current into a load and a pull current that pulls current from the load. When the push current matches the pull current, the output stages are said to be “idling.” The bias voltage controls the idling current.

Abstract: Level shifter circuits are used to configure analog or multilevel memory cells. A level shifter circuit generates an output voltage that is above the input voltage by an offset voltage value. The magnitude of this offset voltage or the relationship between the input and output voltages of the level shifter is adjustable or programmably selectable. Adjustments can be made after the integrated circuits is fabricated and packaged. Adjustments are made by configuring bits of data in the integrated circuit to indicate the offset voltage or other parameters. These configuration bits are implemented using latches, flip-flops, registers, memory cells, or other storage circuits.

Abstract: A charge pump comprises at least one charge pump stage including a first diode having an anode and a cathode, and a capacitor having a first plate connected to the cathode of the diode and a second plate connected to a clock signal that periodically varies between a reference voltage and a supply voltage, the anode of said diode forming a first terminal of the charge pump. The charge pump further comprises a second diode having an anode connected to the cathode of the first diode and a cathode forming a second terminal of the charge pump, first switching means for selectively coupling the first terminal of the charge pump to the voltage supply and second switching means for selectively coupling the second terminal of the charge pump to the reference voltage.

Abstract: An internal power supply voltage generation circuit includes a main amplifier that supplies a current from an external power supply node to an internal power supply line in accordance with the difference between a reference voltage from a reference voltage generation circuit and an internal power supply voltage on the internal power supply line. The current supply amount by the main amplifier is adjusted by a level adjust circuit, according to the difference between the external power supply voltage and the reference voltage. The internal power supply voltage generation circuit can suppress reduction in the internal power supply voltage in the vicinity of the lower limit area of the differential power supply voltage.

Abstract: A method and circuit for automatically centering the control loop bias current by sensing and “memorizing” the total steady state bias current used by the function block (VGA or VCO) through the use of both digital and analog memory elements. The present invention uses an auto-centering, high-impedance current driver to supply the bias current. This current driver cancels out offset currents by exploiting the high output impedance nature of a CMOS current driver using cascoded or resistor source de-generated FET devices.

Abstract: The interface circuit of the present invention is composed to provide: changeover switch 24 that switches between a connection state in which pull-up resistor 23 is connected to input terminal 22 and a connection state in which pull-down resistor 23 is so connected; and microcomputer 26 that discriminates whether it is sink input or source input by discriminating the switch connection state of this changeover switch 24. Moreover, the interface circuit is composed to switch between a signal output state that outputs a signal that is an inversion of the input signal and a signal output state that outputs the input signal as it stands, based on the above discrimination result by this microcomputer 26.

Abstract: A dual current source circuit provides dual currents of the same magnitude and having coefficients of temperature compensation that are also equal but opposite. The core of the circuit is a degenerated differential pair of bipolar junction transistors wherein the base of a first transistor of the pair is connected to a bandgap voltage reference. The base of the second transistor of the pair is connected to a PTAT current source having only one of a positive or a negative coefficient of temperature compensation and a resistor which generates a voltage difference between the bases of the two transistors. This voltage difference generates dual currents, each having equal but opposite coefficients of temperature compensation. A temperature independent stable tail current is provided to the transistors and can be generated by summing the current output of a negative PTAT current source and a positive PTAT current source.

Abstract: A constant voltage circuit having excellent temperature characteristics at a wide temperature range. Temperature characteristics control means constructed by connecting a voltage dividing circuit formed by connecting fixed resistors in series to a diode in parallel is provided between a fixed resistor and a Zener diode having a positive temperature coefficient of a bridge circuit, and the output of a connection point between the fixed resistors of the temperature characteristics control means is applied to the non-inversion input terminal of a differential amplifier to correct the temperature change of the Zener diode.

Abstract: The present invention relates to a booster circuit including a first P-MOS transistor, the source of which is connected to a high voltage line; a second N-MOS transistor, the drain of which is connected to a first supply potential and the source of which is connected to the drain of the first transistor; a first capacitor connected between the gate of the first transistor and a terminal of reception of a first clock signal; a second capacitor connected between the gate of the second transistor and the reception terminal for the first clock signal; a third capacitor connected between the drain of the first transistor and a reception terminal for a second clock signal, complementary to the first clock signal; two precharge diodes the first capacitor from the high voltage line; and one precharge diode for the second capacitor.

Abstract: A bandgap voltage reference circuit wherein a voltage change is induced across one element to compensate for the temperature-induced voltage change across another element. A stable voltage reference is realized across the series combination of the two elements. The circuit includes an operational amplifier, two transistors, a voltage divider and a non-linear temperature-dependent element. The operational amplifier has two input terminals and an output terminal. The voltage divider includes two resistor in series and is coupled to the operational amplifier output terminal. Each of the transistors has a collector corresponding to one of the operational amplifier input terminals, a base corresponding to one of the voltage divider resistor terminals, and an emitter coupled to a common voltage terminal. The non-linear temperature-dependent element is disposed between the voltage divider output terminal providing the lower voltage and the common voltage terminal.

Abstract: A circuit comprising a positive switch and a steering network. The positive switch may be configured to present a first and a second switch signal in response to a first select signal. The steering network may be configured to present a high voltage output that may transition between a very high positive and a very low negative voltage, where the transition may respond to a high positive voltage input, a low negative voltage input, a first and second switch signal, and a second select signal.

Abstract: A regulating system (10) for a charge pump (12) employing a detection sub-circuit (28) and an enable sub-circuit (30) to operate an oscillator (26) and a channel-switching sub-circuit (32) in an automatic manner producing many of the advantages of previously unreconcilable skip mode and constant frequency mode type regulation. The detection sub-circuit (28) compares a feedback signal (52) from the output terminal (18) of the charge pump (12) to a reference signal (56) and produces an error signal (42) representative of output voltage deviation. Concurrently, the enable sub-circuit (30) compares a threshold signal (72) set for a minimum energy quanta which it is efficient for the flying capacitor (24) of the charge pump (12) to transfer to the error signal (42) and produces an enable signal (38) to enable the oscillator (26).

Abstract: The present invention relates to a reference voltage generator circuit for a semiconductor device that enables generating a reference voltage considering various parameters such as temperature variation. There is provided a reference voltage generator circuit coupled between a power supply voltage and a ground voltage for generating a reference voltage responsive to a plurality of current path control signals. A control circuit generates the plurality of the current path control signals. The control circuit includes a voltage division circuit coupled between the power supply voltage and the ground voltage for generating a divided voltage responsive to a plurality of externally applied code signals. A comparison circuit compares the divided voltage and the reference voltage and generates a comparison signal as a result of the comparison.

Abstract: There is disclosed a semiconductor device in which capacitor means are connected to multiple input terminals via latch means, and the terminals on one side of the capacitor means are commonly connected to the input of a sense amplifier, thereby attaining a reduction of the circuit scale, improvement of the operation speed, saving of the consumption power, reduction of the manufacturing cost, and improvement of the manufacturing yield.

Abstract: A current reference generator comprises a pair of identical units (G1, G2) which generate respective current references (I1, I2), and a circuit (CL) for the linear combination of the two references. In each of the two units, the elements (S1, S2) which, by their current-voltage characteristics, determine the working point comprise respectively a single transistor (T1) and a pair of transistors (T2, T3), of the same type as the first, connected in series. A differential amplifier (AD) maintains stable the working point of the respective unit as power supply voltage varies. (FIG.

Abstract: A circuit arrangement (100) is coupled to a resistor (150) having at least two portions (110, 120). The arrangement (100) provides a substantially linear performance of the resistor (150). The arrangement (100) comprises a differential difference amplifier (160) (with input stages (170, 180) and output stage (190)) and a feedback unit (130). The input stages (170, 180) modify first (161) and second (162) measurement signals (e.g., (V.sub.B -V.sub.A) and (V.sub.A -GND), respectively) from the resistor portions (110, 120) to intermediate signals (OPH, OMH, OPL, OML). The output stage (190) differentially amplifies sums (at nodes 191, 192) of the intermediate signals and provides a control signal (CONTROL) which corresponds to a magnitude difference between the first and second measurement signals. The feedback unit (130) receives the control signal and supplies a corrective current (I) to the resistor (150) to offset non-linearity.

Abstract: A charge pump circuit includes MOS capacitors configured to operate in the accumulation region, resulting in a substantially constant capacitance over the operational range. In a particularly preferred embodiment, a char ge pump uses multiple stages of p-channel MOS capacitors. In accordance with a further aspect of the present invention, oxide thicknesses of the p-channel MOS capacitors are optimized in accordance with the requirements of each stage.

Abstract: In a non-volatile memory capable of electrically rewriting data, a timer circuit for determining writing time that is operable at any time at a voltage of under 1.0 V. The timing circuit has a regulated voltage circuit for outputting a regulated output voltage no greater than 1.0 V, a constant current circuit for producing a constant current having a value determined by the regulated output voltage, a voltage comparing circuit for comparing an input voltage input to one terminal with a reference voltage input to another terminal, and a capacitive element connected to a constant current output terminal of the constant current circuit.

Abstract: A scaleable charge pump. The charge pump is configured on an integrated circuit device that operates at a supply voltage and includes a predetermined number of pump stages coupled in series, at least one of the stages being coupled to receive a first pumped clock signal. An output node coupled in series to one end of the predetermined number of series coupled pump stages provides a pumped output voltage.