Abstract: The present invention relates to a semiconductor integrated circuit having function blocks with differing operating frequencies and to a semiconductor integrated circuit wherein the threshold voltages of MOS transistors that configure these function blocks are different for each function block. In first to Nth function blocks (30-1 to 30-N), which are supplied with constant voltages (VC1 to VCN) generated by a constant voltage generation section (20) as power voltages, any variation in operating speed or in the capability of the transistors is detected by an operating state detector (40) as a voltage (Vfre). Further, an operating state encoding section (50) encodes the voltage (Vfre), a voltage output control section (60) modifies basic voltages (VB1 to VBN) of the constant voltage generation section (20), and constant voltages (VC1 to VCN) for the function blocks (30-1 to 30-N) is modified.

Abstract: Bias circuitry is configured to adjust bias current to one or more power amplifier stages based upon the level of the RF signal to be amplified. A feed-forward circuit senses the input power level of the signal to be amplified and dynamically adjusts the bias current for one or more amplifiers in the amplification path to ensure each amplifier is operating in a linear region for the given signal level. For amplifier configurations having multiple amplification stages, the bias circuitry provides proportional bias currents to each stage as necessary for the progressively increasing signal levels being amplified. The bias circuitry eliminates excessive quiescent bias currents that prior biasing techniques required to ensure linear operation by automatically increasing bias currents only as needed based on the effective magnitude of the RF signal to be amplified.

Abstract: An IC comprises a pair of circuit nodes, a current mirror that includes dual-function transistor, and a controller for switching the transistor between a pair of states. In a first state, the transistor provides current gain and also provides a relatively high impedance between the nodes, and in a second state, it provides no current gain and a relatively lower impedance between the nodes.

Abstract: A method for minimizing instantaneous currents ina signal bus is disclosed. The method involves providing a programmable delay element in each of the signal buffers driving the signal on the bus. The programmable delay element in each signal buffer is selectable enabled to include a predetermined time delay. The method involves programming the delay elements in a selected group of the signal buffers t includde the predetermined time delay, so that the selected group of signal buffers each generate an output signal switching after the predetermined delay relative to the switching of output signals generated by other signal buffers.

Abstract: The present invention comprises a method and apparatus for boosting an input signal to an output signal with a variable gain according to a supply voltage. The circuit comprises a detector and a voltage booster. The detector detects the supply voltage and generates a control signal having a value dependent on a difference between the detected supply voltage and a critical supply voltage. The critical supply voltage is temperature insensitive. The voltage booster is coupled to the detector for generating an output signal having a gain relative to the input signal. The gain is dependent on the value of the control signal.

Abstract: A system and method for a supply-independent VCO biasing scheme for generating bias voltages and currents for a VCO of a phase-locked loop are disclosed A biasing scheme for generating a bias electrical signal comprises a first and second current source coupled to a power supply, a current drain coupled to the second current source and to ground, a replica device having a first node, a second node coupled to the second current source and the current drain, and a third node coupled to ground, and a first and second current splitting device having first nodes coupled to each other and to the current source and having third nodes coupled to the first and second nodes of the replica device, respectively.

Abstract: The circuits and methods of the present invention provide rail-to-rail output stages that cancel the non-linear components of the transconductances of transistors used in the output stages, that allow the idling current in the output stages to be controlled by external current sources and device size ratios, and that enable the idling current in the output stages to be maintained independently of manufacturing processes, temperature, and power supply voltages. The output stages generally comprise a complementary subcircuit, a current mirror and an output driver. The output stages receive an input signal and a bias voltage from an external source and responsively produce a push current that feeds current into a load and a pull current that pulls current from the load. When the push current matches the pull current, the output stages are said to be “idling.” The bias voltage controls the idling current.

Abstract: A voltage boosting circuit of a semiconductor device is disclosed. The voltage boosting circuit includes a voltage detector, an active kicker controller, and an active kicker. The voltage detector generates a detection signal after the determining whether a potential of the signal to be boosted is higher than a boost voltage target level. The active kicker controller generates an active kicker control signal in response to the detection signal and the clock signal. The active kicker drives the signal to be boosted in response to the active kicker control signal. The voltage detector includes a current source, a number of switching devices, a current compensating circuit, and an inverter circuit. The current compensating circuit provides a compensating current proportional to a power supply voltage.

Abstract: There is provided a level shift circuit which includes an input terminal for receiving a logic input signal changing between a first voltage and a reference voltage. An output terminal provides a logic output signal changing between a second voltage and the reference voltage. A pull-up transistor has a control electrode and a pair of controlled electrodes. The controlled electrodes are coupled between the second voltage and the output terminal. A pull-down transistor has a control electrode and a pair of controlled electrodes. The control electrode of the pull-down transistor is coupled to the input terminal, and the controlled electrodes of the pull-down transistor are coupled between the reference voltage and the output terminal. A charge/discharge circuit charges the control electrode of the pull-up transistor with the second voltage when the logic input signal is changed from the reference voltage to the first voltage.

Abstract: An on chip voltage generation circuit is provided suitable for use on integrated circuits such as flash memory devices with a low power supply voltage (e.g., 2.7 to 3.6 volts). A voltage boost circuit is coupled to the supply voltage input and to a boost signal, which boosts the on-chip voltage at a node on the integrated circuit in response to a transition of the boost signal. The voltage boost circuit has a first mode which in response to the transition boosts the on-chip voltage at a first rate of boosting until a first threshold, and a second mode which in response to the transition boosts the on-chip voltage at a second rate of boosting until a second threshold. The second rate of boosting in the preferred system is slower than the first rate of boosting. A detection circuit is coupled to the node on the integrated circuit which receives the on-chip voltage, and to the voltage boost circuit.

Abstract: A circuit that senses changes in the electrical characteristics of one or more circuit elements and generates one or more signals based, at least in part, on the electrical characteristics that are sensed, is incorporated into an integrated circuit. In a further aspect of the present invention, the one or more signals generated by the circuit are indicative of the reliability of an electronic device into which an embodiment of the present invention is incorporated.

Abstract: A power-up circuit for a multi-voltage chip having two or more electrostatic devices coupled in series between first and second power supply lines, with a first electrostatic device being coupled between a node and the second power supply line. The power-up circuit comprising a MOS transistor coupled between the first power supply line and the node. A voltage divider coupled between the first and second power supply lines controls the conductivity of the MOS transistor. An internal node of the voltage divider is coupled to the gate of the MOS transistor and the divider is configured such that the internal node rises in potential following power-up to regulate the conductivity of the MOS transistor. The MOS transistor changes from a high conducting state to a low conducting state responsive to an increase in potential of the second power supply line following power-up.

Abstract: A multi-driving apparatus by a multi-level detection which pluralizes a voltage detection level in order to effectively operate voltage generators in the voltage generation circuit, minimizes a level fluctuation, reduces noise influenced on a total operation of the apparatus, increases a reliability of the apparatus, and reduces the power-consumption.

Abstract: In one embodiment, a semiconductor circuit includes a first group of field effect transistors having a body and parameters including a net channel doping level DL1. The circuit also includes a conductor to provide a first voltage to the body to forward body bias the first group of transistors, the first group of transistors having a forward body bias threshold voltage (VtFBB) when forward body biased, wherein DL1 is at least 25% higher than a net channel doping level in the first group of transistors that would result in a zero body bias threshold voltage equal to VtFBB, with the parameters other than the net channel doping level being unchanged. In another embodiment, the semiconductor circuit includes a first circuit including a first group of field effect transistors having a body.

Abstract: A bandgap-based reference voltage generator circuit with an increased output reference voltage and a reduced temperature coefficient uses a curvature correction bias voltage to significantly reduce the degree of variation of the bandgap-based reference voltage over temperature. A current having a negative temperature coefficient is conducted by a resistor having a positive temperature coefficient. The resultant voltage across the resistor has an arcuate voltage-versus-temperature characteristic with a direction of incurvature that is substantially opposite the direction of incurvature of the corresponding arcuate voltage-versus-temperature characteristic of the voltage generated by a conventional bandgap reference voltage generator circuit. These voltages are summed together to produce a bandgap-based reference voltage which is greater in magnitude than a conventional bandgap reference voltage and has a significantly reduced temperature coefficient.

Abstract: First and second buffer circuits generate first and second reference potentials. A switching circuit selects a first reference potential as a reference potential while a sense operation is not performed and selects a lower second reference potential while the sense operation is performed. A buffer circuit is controlled such that a through current increases only for a predetermined time period at a initiation and a termination of the sense operation.

Abstract: A reference voltage output by a bandgap voltage reference circuit is formed by summing an amplified voltage that has a positive temperature coefficient with a base-to-emitter voltage that has a negative temperature coefficient. The amplified voltage is formed by amplifying a difference voltage &Dgr;VBE. Variations over temperature of the reference voltage are reduced by increasing the magnitude of the difference voltage &Dgr;VBE. By increasing the magnitude of the difference voltage &Dgr;VBE, a smaller gain can be used to form the amplified voltage. By utilizing a smaller gain, less of the error associated with the difference voltage &Dgr;VBE is present in the amplified voltage.

Abstract: A regulation circuit for regulating an output voltage of a positive charge pump for an integrated circuit includes a comparison circuit receiving a reference voltage at an input, and delivering an enabling signal at an output to the positive charge pump. The regulation circuit further includes a first switching circuit controlled by a first control signal for the application of a first voltage level as a reference voltage when the integrated circuit is in an operational mode, and the application of a second voltage level as the reference voltage when the integrated circuit is in a standby mode.

Abstract: An internal power-source potential supply circuit for supplying an internal power-source potential with high accuracy is disclosed. An external power-source potential (VCE) is connected to the source of a PMOS transistor (Q1) having a drain for applying an internal power-source potential (VCI) to a load (11) and a gate receiving a control signal (S1) from a comparator (1). The comparator (1) outputs the control signal (S1) on the basis of a comparison result between a reference potential (Vref) and a divided internal power-source potential (DCI). The drain of the PMOS transistor (Q1) is connected to a first end of a resistor (R1), and a current source (2) is connected between a second end of the resistor (R1) and ground. A voltage provided at a node (N1) serving as the second end of the resistor (R1) is applied to a positive input of the comparator (1) as the divided internal power-source potential (DCI).

Abstract: An apparatus comprising a first circuit, a second circuit and a third circuit. The first circuit may be configured to generate a first current in response to a first input signal. The second circuit may be configured to generate a second current in response to a second input signal. The third circuit may be configured to present a first pulse of current at a first output or a second pulse of current at a second output in response to the first and second currents.