Abstract: Methods and apparatus are provided for hot swapping a hard disk drive. A gateway is connected between the disk drive and the bus leading to the host adapter. The gateway can isolate the disk drive from the bus prior to a disk drive being removed and can signal to the host adapter when a new drive has been installed. The gateway can de-isolate the newly installed disk drive from the bus to allow the host adapter to communicate with the newly installed disk drive. Additionally, the gateway can remove system power from a disk drive being removed and ramp up power to a newly installed disk drive while system power is uninterrupted for other components of the computer system. An adapter may be provided to connect a disk drive to the gateway, and the gateway and the adapter engage and/or disengage during the hot-swapping of the disk drive.

Abstract: A method and apparatus for controlling access to a plurality of resources based on multiple received requests is provided. The system includes a priority register configured to receive each individual request, determine a priority for the request, and transmit the request to a priority appropriate path. A first high priority arbiter receives and arbitrates among highest priority requests in a round robin manner to determine a high priority suggested grant vector. At least one lower priority arbiter receiving and arbitrating among lower priority requests in a round robin manner to determine at least one lower priority suggested grant vector. Grant circuitry passes the high priority suggested grant vector unless said grant circuitry receives a low priority indication, whereby the grant circuitry passes a lower priority grant vector.

Abstract: A system and method for enabling Intellectual Property (IP) Blocks to be reused at a system level. The present invention represents the IP blocks as blocks that exchange messages without needing to represent the functionality of the IP blocks. The implementations of these IP blocks exchanges messages through complex signaling protocols. In conventional systems, interfacing between IP blocks that use different signaling protocols is a tedious and error prone design task. The present invention uses regular expression based protocol descriptions to show how to map the message onto a signaling protocol. Given two protocols, the present invention builds an interface machine that automatically labels data referenced by all protocols. The present invention is capable of generating the interface even when the data sequencing of the two protocols differs.

Abstract: A system to monitor performance of a computing device includes a first bridge to interface with a first set of devices, and a second bridge to interface with a second set of devices. Configuration registers store configuration data associated with the second set of devices, and are accessible through the second bridge. A hub interface allows data to transfer downstream from the first bridge to the second bridge, and allows data to transfer upstream from the second bridge to the first bridge. A controller, external to the first and second bridges, accesses the configuration registers via the second bridge. A logic device allows the second bridge to send data to, and receive data from, the controller.

Abstract: A method and architecture optimizes transaction ordering in a hierarchical bridge environment. A parent-bridge is one level above a child-bridge, which in turn is one level above a grand-child component. The parent-bridge is a bridge-bridge. The child-bridge can be a bus-bridge or a bridge-bridge. The grand-child component can be a bus, a bus-bridge or a bridge-bridge. A parent-bridge is connected to a child-bridge via child-links, the child-bridge connected to grandchild-links, and the parent-bridge having multiple transaction order queues (TOQs) per child-link. Ideally, the parent-bridge has one TOQ for each grandchild-link where the parent-bridge applies separate transaction ordering for each of the grandchild-links. However, at a minimum, the system uses at least two TOQs per child-link, and as such, provides a higher level of transaction throughput than systems using one TOQ per child-link. The child-bridge sends a signal to the parent-bridge identifying from which grandchild-link a transaction was sent.

Abstract: A communications module for a data communications system having a plurality of data processors comprises a plurality of ports, each coupled to a respective one of the data processors. An address table associates addresses of a memory space to addresses of the data processors. The memory space may include addressable FIFOs, SRAM memory and/or flag registers. In the case of FIFOs, a counter coupled to the FIFO supplies a flag or ready signal indicating the not-full or not-empty status of the respective FIFO, which is supplied to a master device that is writing data to the FIFO or that is reading data from the FIFO so that the writing master device will write only when the FIFO is not full and the reading master device will read only when the FIFO is not empty.

Abstract: A configurable bus interface circuit includes an internal bus bridge and an internal circuit. The configurable bus interface circuit also includes an internal I/O circuit couplable to an external circuit, via the internal bus bridge. The configurable bus interface circuit electrically isolates the internal circuit to avoid the propagation of signals between the internal I/O circuit and the external circuit.

Abstract: The present invention relates to a method of operating a crossbar switch (1) having a control logic (2) and n input ports (i—0, . . . , i_n-1) and m output ports (o—0, . . . , o_m-1), wherein information packets of p different priority levels are routed from said n input ports (i—0, . . . , i_n-1) to said m output ports (o—0, . . . , o_m-1). Within said control logic (2), a pool (CRA) of buffers (CRA—0, CRA—1, . . . ) is provided for each crosspoint (4) for temporarily storing address information related to said information packets.

Abstract: Once attached to a slot of a personal digital assistant, a card module executes an application-specific program and transmits a result obtained thereby to the personal digital assistant. The thus received execution result is outputted from an output part. Accordingly, the output part can be provided for shared use among several card modules for output of the execution result.

Abstract: A resource and partition manager of the preferred embodiments includes a lock mechanism that operates on a plurality of locks that control access to individual hardware resources. The resource and partition manager uses the lock mechanism to obtain a lock on a hardware resource when transferring control of the hardware resource to a logical partition that is powering on and when removing the hardware resource from a logical partition that is powering off. The resource and partition manager uses the lock mechanism to remove control of a hardware resource from, or return control to, an operating logical partition in order to facilitate hardware service operations on that hardware resource or on the physical enclosure in which it is contained.

Abstract: In a programmable fixed priority and round-robin arbiter and a bus control method of the same, the arbiter includes, an HPRIF rotating unit, a request-reordering unit, a request-selecting unit, and a grant-reordering unit. In the fixed priority mode or the round-robin mode, the HPRIF rotating unit rotates priority information related to bus masters stored in a predetermined register in a predetermined direction to give the highest priority to a bus master in response to pointer information and outputs changed priority information. When a request signal is received from the bus masters, the request-reordering unit reorders requested priorities of the bus masters to be in accordance with the changed priority information and outputs a request-reordering signal. The request-selecting unit outputs a bus master-selecting signal according to priorities in response to the request-reordering signal.

Abstract: Access to a bus is granted to one of a number of requesting communication circuits that each submitted a bus control request during a request period of an arbitration period in response to the entries in a priority table. If a requesting communication circuit has an identity and priority that match the identity and priority of a communication circuit stored in a row of the priority table that corresponds with the arbitration period, access to the bus is granted to the requesting communication circuit.

Abstract: A method and apparatus to facilitate a history trace of system bus activity in a Symmetric Multi-Processor (SMP) environment. A dynamic scan capability is provided to User (516) via Computer (504) that allows dynamic configuration of History Control Register (518), thus providing a maskable history stack of system bus activity to be obtained from History Memory (508) for subsequent analysis.

Abstract: A method and apparatus are disclosed for allowing a plurality of network connectors to utilize a single network controller within a docking station or portable device. A switching device connects the plurality of network connectors with the network controller. By connecting the network connectors into the switching device, the docking station and the portable device require a single network controller to handle the network communication. The switching device enables the network controller to continue to operate without disrupting the portable device when the network connection is changed from the docking station to the portable device or vice versa. The method and apparatus are useful in reducing the complexity of the total system while increasing functionality.

Abstract: The present invention provides an apparatus and method for selecting bus-width formats. In an exemplary preferred embodiment of the invention, the circuit includes a bus controller configured to provide a first bus-width control signal to select a first bus-width. The circuit also includes a bus controller extension circuit configured to force the first bus-width control signal to a predetermined level when the bus controller is applied to a bus with a second bus controller that is incompatible with the first bus-width. Advantages of the invention include controlling a number of data bits to be transferred between a PCI device and a data bus that does not violate PCI specifications. Other advantages include a programmability of the PCI device to adapt to legacy systems as PCI technology progresses.

Abstract: A system and method for generating sequences of triggered events and for generating global interrupts in a clustered computer graphics system. In a sender-receiver dichotomy, one node is deemed the sender and the others act as receivers. The sender determines trigger values for each of the nodes in the system in order to achieve a particular operation sequence. In addition, a synchronization signal generator is provided to synchronize a timing signal between the sender and receiver nodes. Further, the sender designates one or more receiver nodes and causes them to turn on an interrupt enable register. In this way, the receiver nodes are able to be interrupted by the sender.

Abstract: An incremental or bit by bit address decode scheme allows each device on a serial bus to determine as soon as possible if it is the device being addressed by a master device. As each address bit is received serially into a device, it is immediately compared with a corresponding bit of the device's address. As soon as there is a bit not matching, the device in question is determined to not be the one addressed by the master device. It can then be disengaged from the communication process and free up as soon as possible its internal resource initially reserved for possible access by the master device.

Abstract: A system for transmitting and receiving data formatted in IEEE 1394 standard between devices using a same IEEE 1394 broadcast channel includes a CPU interfaced to a bus, a first 1394 interface connected to the bus via a first physical and link layers, and a second 1394 interface connected to the bus via a second physical and link layer. The CPU is configured for 1) receiving data from the bus, prefixing a header to the received data, and retransmitting the received data with the prefixed header onto the bus; and 2) receiving data prefixed with a header, interpreting the header to identify which of the first or second interfaces should receive the data, and transmitting the data over the bus to the identified 1394 interface.

Abstract: This invention is to provide a PC switching device which can be applied to various kinds of PC's, some of which have an electric power control method different from the others. When a plurality of PC's 621–624, the power of which are controlled by power control keys installed on keyboards are operated by single KB 63 without a power control key, power control switches PC-PSW 1–4 installed on the PC switching device 61 can control the power of the corresponding PC. When switches PC-PSW 1–4 are pressed again, main CPU 610 outputs a key-code to PC's 621–624 through sub-PC's 611–614, and can control the power of PC's.

Abstract: A read-write interface system and method for a peripheral device includes storing data to be processed by a peripheral device; receiving a set of input data bits; transferring the set of input data bits from the shift register to the latch circuit in a write operation; accessing a leading bit of the set of input data bits from the latch circuit in advance of a read operation; and enabling in a read operation the rest of the input data bits in the latch circuit to be transferred to the shift register to be output with the leading bit.