Abstract: A method, apparatus, and computer program product are described for controlling data transfer. A next data packet to be transferred is retrieved. A determination is made regarding whether a data bus busy signal is asserted. If the data bus busy signal is asserted, a determination is made regarding whether a data bus grant signal is asserted. If the data bus grant signal is asserted, the next data packet is transferred on the next cycle after a last cycle of data transfer of a previous data packet.

Abstract: A portable computer can be “hot” docked to one or more expansion devices, such as a drive wedge and a port replicator. As such, the expansion devices can be connected to and disconnected from the portable computer while portable computer is powered on and fully operational. The portable computer includes control logic that detects when an expansion device is connected to or disconnected from the portable computer and asserts an SMI or equivalent interrupt signal to the computer's CPU to initiate a sequence of events by which the computer determines whether an expansion device has been connected or disconnected. If the CPU determines that the expansion device has been connected to the computer, the CPU appropriately reconfigures itself to communicate with the expansion device. If the expansion device is disconnected, the CPU also appropriately reconfigures itself to preclude communications with the disconnected device.

Abstract: A bus routing strategy for a printed circuit board is disclosed. The routing strategy ensures that traces coupled to a plurality of synchronous devices are not routed through the center region of each package, ensures that each trace in a bus is approximately the same length, minimizes the length over which “neckdown” occurs, and ensures that traces are routed without making sharp turns. By using this routing strategy, propagation time differences within each trace group are minimized. Also, the center regions of the printed circuit board under each package are available for vias connected to bypass capacitors.

Abstract: An expansion module for a Handspring Visor includes a multi-master AMBA Advanced System Bus (ASB). The Springboard bus of the visor is coupled to the ASB bus via Springboard-to-ASB-bus bridge. This bridge includes a protocol translator and a second Arm7 to ASB interface. The protocol translator translates bi-directionally between the Springboard bus protocol and the Arm7TDMI protocol. The translator includes an interface to the Springboard bus and a state machine. The state machine coordinates data transfers between the buses. The state machine also monitors signals indicating when each of the buses begins to treat a data transfer as complete so that the data transfer can be validated or flagged as an error condition. A programmable counter adjusts maximum counts to compensate for different clock frequencies in measuring a write-wait state duration to ensure valid writes from the Visor to the ASB bus.

Abstract: A transaction tracing circuit for use with a bus bridge that is couplable to at least a first and second bus. The transaction tracing circuit includes at least one set of trace control registers that is associated with a transaction tracing function for tracing a specific transaction occurring on the bus bridge. A number of bus transaction tracing circuits, one for each bus to which the bridge is connected, are coupled to the trace control registers and are utilized to store is transactions that are captured as they occur on the individual buses. An internal transaction tracing circuit is coupled to the trace control registers and is utilized for storing captured internal transaction information corresponding to the specific internal transaction.

Abstract: The present invention utilizes a file locking emulator between an application program and an operating system. The file locking emulator comprises an application program interface and a file lock supervisor. The file locking emulator receives the file locking requests from the application program and generates file requests and file lock query commands. When the application program interface receives a file request it first checks the files lock status and then either returns an error for incompatible file requests or executes the compatible lock request along with any other compatible operation request such as a read, write or truncate file operation. Only code in the file request emulator needs to be rewritten when an application program is ported to different operating systems sharing incompatible but executable processes. In this manner tested code of the application program does not have to be rewritten.

Abstract: A memory card (1) includes an electrically rewritable non-volatile memory (4), a data processor (3) having a function of executing instructions and managing the allocation of file data in the non-volatile memory, an interface control circuit (2) having a function of establishing an external interface, for controlling the execution of instructions by the data processor in response to external commands and for controlling access to the non-volatile memory and a buffer memory (7) for temporarily storing the file data. The interface control circuit includes command control means for decoding a first command externally supplied and for instructing the data processor to fetch an instruction from the buffer memory and to operate.

Abstract: In a bridged, pipelined network (FIG. 1), a network-to-host bridge (140) identifies the address space of a host computer (FIG. 2) as not being contained within the host computer memory space (120). During the removal of the host computer (100) and its replacement by a new host computer, the network-to-host bridge (140) momentarily locks out traffic (FIG. 3, step 320) in order to disable peripheral components (FIG. 1, 160, 180) from initiating bus transactions. When the new host computer is installed (FIG. 3, step 320) and the bus lockout is removed (step 340), the new host memory area is protected from direct memory access transactions which were stored in the bus hierarchy during the host computer swap.

Abstract: A multi-stage byte lane selectable bus. In a preferred embodiment, the bus in performance monitor mode includes a plurality of byte lanes and a selection mechanism. The selection mechanism acquires, from a plurality of signals, a subset of those signals, which are desired to be monitored, and places this subset of signals on the byte lanes that are input to the PMU. The number of the plurality of signals that potentially may be monitored is greater than the number of byte lanes and is also greater than the number of PMU counters.

Abstract: Computer system configuration resources include first and second control circuits in respective first and second integrated circuits. A communication link, which transfers data over a plurality of logical pipes, connects the two integrated circuits. Configuration of the link utilizes a link bridge that includes upstream (located closest to the CPU) configuration registers that are within the first control circuit and downstream ((located farthest from the CPU) configuration registers within the second control circuit. A link header, which includes upstream data for the first control circuit and down stream data for the second control circuit, is used to initialize the link. The upstream and downstream data may include information specifying the size of the communication link.

Abstract: A host controller, such as a host controller for a Universal Serial Bus, may process isochronous and interrupt transfers on a preferential basis. If time permits, bulk and control transfers may be executed. The bulk and control transfers may be executed in queues having a queue context made up of a queue head and one or more transfer descriptors. These queues may be processed one after another in a circular linked list. By uniquely marking an element in the circular linked list and determining the status of the transfer operation, the host controller can be avoid thrashing the bus when the reclaim list is empty.

Abstract: A high-speed bus subsystem includes a plurality of bus channels, wherein each bus channel has an independent channel clock signal generated by an associated channel clock generator. A master device or other interface component receives and utilizes a system clock signal and a channel clock signal for each channel. For each channel, a derivative of the system clock signal and a derivative of the channel clock signal are routed to a clock generator. The clock generator compares the received signals, and generates its channel clock signal at a phase which eliminates any significant phase difference between the system clock signal and the channel clock signal.

Abstract: In a computing system with non-shareable resources, use-arbitrating processes are executed on behalf of each task seeking or having access to non-shareable resource. The processes compete according to prescribed rules and priority guidelines, the resolution of which determines access to the non-shareable resource. If application of the priority guidelines permits, a use-requesting task can institute takeaway of a resource from a task that is already using the resource.

Abstract: A system is disclosed for allowing surprise insertion and removal of a peripheral device from the bays of a portable computer system. The peripheral device may be inserted or removed when the portable computer system is powered off, powered on, or in standby or sleep mode. The peripheral device may be any one of a multitude of devices corresponding to the IDE, ATAPI or FLOPPY standard. Insertion or removal of the device is operating system and BIOS independent. A constantly executing detection process determines when a peripheral device has been inserted into or removed from a bay. A multilevel device driver allows layered functionality and simplified interfacing between the operating system and computer system and peripheral hardware. Identification and configuration of the peripheral device is handled by a IDE/ATAPI bridge device driver that is capable of recognizing any IDE, ATAPI or FLOPPY device inserted into a bay.

Abstract: A method and system for eliminating peripheral device conflicts in a multibus data-processing system which includes a Peripheral Component Interconnect (PCI) plus having multiple slots for interconnecting peripheral devices in an automatically derived configuration and an Industry Standard Architecture (ISA) bus having multiple slots for interconnecting peripheral devices in a user-selected configuration. Each slot included within the ISA bus includes a reset line for temporarily disabling an associated slot in response to an application of electrical power to the data-processing system in order to prevent power transition problems. In response to an existing or potential device conflict brought about by a user-selected configuration, a control signal is selectively applied to the reset line for one or more slots included within the ISA bus, temporarily disabling those slots during normal operation of the data-processing system.

Abstract: A system transfers BIOS instructions from a BIOS ROM to a processor for either execution or storage in a system memory. The BIOS ROM has an address bus coupled to an address bus of the processor and a data bus coupled to the an intelligent drive electronics (“IDE”) controller through the data bus portion of an IDE bus. In operation, the processor applies addresses directly to the address bus of the BIOS ROM, and the corresponding instructions are coupled through the IDE data bus and the system controller to the data bus of the processor.

Abstract: A multiprocessor system bus protocol system and method for processing and handling a processor request within a multiprocessor system having a number of bus accessible memory devices that are snooping on. at least one bus line. Snoop response groups which are groups of different types of snoop responses from the bus accessible memory devices are provided. Different transfer types are provided within each of the snoop response groups. A bus master device that provides a bus master signal is designated. The bus master device receives the processor request. One of the snoop response groups and one of the transfer types are appropriately designated based on the processor request. The bus master signal is formulated from a snoop response group, a transfer type, a valid request signal, and a cache line address. The bus master signal is sent to all of the bus accessible memory devices on the cache bus line and to a combined response logic system.

Abstract: A microprocessor includes a first bus and a second bus capable of operating simultaneously, a single port memory divided into a plurality of banks, a bus switch circuit provided between the plurality of banks and the first and second buses, and a processor core connected to the first and second buses and the single port memory. The bus switch circuit may be controlled statically, independent of activities on the buses, or may be controlled dynamically according to the activities.

Abstract: A first embodiment of the present invention includes a decoder 320 and a detection circuit 330. The decoder 320 receives data at a packet rate. Each packet includes more than one word so that the packet rate is less than a word rate. The detector circuit 330 monitors a data valid signal from the decoder 320 and asserts an output signal (send idle) upon determination that the data valid signal changes values at a rate higher than the packet rate.

Abstract: A method for transmitting ordered packets on a bus within a data processing system is disclosed. A data processing system includes a bus connected between a bus master and a bus slave. The bus master consecutively issues multiple packets, such as command packets, to the bus slave on the bus. The packets include order sensitive packets and non-order sensitive packets. In response to a temporary inability of the bus slave to process a particular one of the order sensitive packets due to a lack of resources, the bus slave keeps retrying the particular order sensitive packet. When resources become available, the bus slave processes the retried order sensitive packets in order while allowing the retried non-order sensitive packets to be processed in any order.